GPIO default state before FPGA configuration (weak pull-up vs. pull-down)

Between power-on and FPGA configuration, the GPIO pins are in a tristate condition with a weak pull-up enabled. As a result, the device’s digital outputs are initially driven HIGH and only switch to their intended state (LOW) after the FPGA configuration is complete.

This behavior is causing problems for downstream signal evaluation.

Questions:

• Is it possible to modify this default behavior of the GPIO pins before configuration?
• Specifically, can a pull-down (instead of a weak pull-up) be configured or enforced during the pre-configuration phase?

Any guidance or recommended solutions would be appreciated.