IP components used in the design have conflicting settings. Intel PCIE Ftile MCDMA

Question

I generated a 4x4 PCIE MCDMA using the ip designer using quartus 25.3.0.109 from the example design from https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-agx7m-hbm2e/#pcie-bam-interface. I then switched my design to use a 1x16 port and I got this error.

Error (21842): Support logic cannot be generated because IP components used in the design have conflicting settings

Error (21843): Conflict 0 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip8::constraint_powerdown_mode @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core8

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core8_powerdown_mode) == FALSE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core8_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core8_pf0_subclass_code == 4

Error (21843): ctop_core8_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 1 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip4::constraint_powerdown_mode @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_1_powerdown_mode) == FALSE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_1_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core4_1_pf0_subclass_code == 4

Error (21843): ctop_core4_1_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 2 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip4::constraint_powerdown_mode @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_0_powerdown_mode) == FALSE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_0_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core4_0_pf0_subclass_code == 4

Error (21843): ctop_core4_0_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 3 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip4::ipd_powerdown_rules @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_0_powerdown_mode) == FALSE || gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.func_mode == DISABLE

Error (21843): Rule: gdrb_gdr_pcie_ip4::pf0_subclass_code_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.func_mode == ENABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_0_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core4_0_pf0_subclass_code == 4

Error (21843): ctop_core4_0_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 4 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip4::constraint_powerdown_mode @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_0_powerdown_mode) == FALSE || gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.func_mode == DISABLE

Error (21843): Rule: gdrb_gdr_pcie_ip4::pf0_subclass_code_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.func_mode == ENABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_0.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_0_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core4_0_pf0_subclass_code == 4

Error (21843): ctop_core4_0_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 5 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip4::ipd_powerdown_rules @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_1_powerdown_mode) == FALSE || gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.func_mode == DISABLE

Error (21843): Rule: gdrb_gdr_pcie_ip4::pf0_subclass_code_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.func_mode == ENABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_1_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core4_1_pf0_subclass_code == 4

Error (21843): ctop_core4_1_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 6 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip4::constraint_powerdown_mode @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_1_powerdown_mode) == FALSE || gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.func_mode == DISABLE

Error (21843): Rule: gdrb_gdr_pcie_ip4::pf0_subclass_code_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.func_mode == ENABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core4_1.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core4_1_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core4_1_pf0_subclass_code == 4

Error (21843): ctop_core4_1_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 7 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip8::ipd_powerdown_rules @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core8

Error (21843): (gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.powerdown_mode -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core8_powerdown_mode) == FALSE || gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.func_mode == DISABLE

Error (21843): Rule: gdrb_gdr_pcie_ip8::pf0_subclass_code_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core8

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.func_mode == ENABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core8_pf0_subclass_code) == 0

Error (21843): Input variables:

Error (21843): ctop_core8_pf0_subclass_code == 4

Error (21843): ctop_core8_powerdown_mode == TRUE

Error (21843): is_used == TRUE

Error (21843): Conflict 8 ----------------------------------------------------------------

Error (21843): Rule: gdrb_gdr_pcie_ip8::pf0_subclass_code_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core8

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.func_mode == ENABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_subclass_code -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core8_pf0_subclass_code) == 0

Error (21843): Rule: gdrb_gdr_pcie_ip8::pf0_usp_tx_preset0_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core8

Error (21843): gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.func_mode == DISABLE || (gdr.z1577b.u_pcie_ss.u_ctop.ub_core8.pf0_usp_tx_preset0 -> u0|subsys_pcie_0|intel_pcie_ftile_mcdma_0|intel_pcie_ftile_mcdma_0|ast_hip|intel_pcie_ftile_ast_hip|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_pcie_inst.ctop_core8_pf0_usp_tx_preset0) < 11

Error (21843): Input variables:

Error (21843): ctop_core8_pf0_subclass_code == 4

Error (21843): ctop_core8_pf0_usp_tx_preset0 == 15

Error (21843): is_used == TRUE

Error: Design cannot be programmed onto available F-Tiles because given location constraints are conflicting, or because the design requires more resources compared to what is available on current device

Error: Quartus Prime Logic Generation Tool was unsuccessful. 86 errors, 129 warnings

Error: Peak virtual memory: 5368 megabytes

Error: Processing ended: Mon Jun 22 11:02:57 2026

Error: Elapsed time: 00:01:01

Error: System process ID: 3346668

Attached is the project file archive and qsys.

vent_altera · Answer

Hi BeJamInThank you for reaching out to us.Could you please regenerate the MCDMA IP from scratch using the 1x16 IP mode configuration? Instead of modifying the existing 4x4 MCDMA IP, please create a new MCDMA IP instance in Platform Designer and select 1x16 during the initial IP configuration. The reason for this recommendation is that changing the IP mode from 4x4 to 1x16 through the GUI may not fully reset the internal parameters associated with the unused sub-cores, which could lead to unexpected behavior.Please let me know whether the issue persists after regenerating the fresh IP for 1x16 mode configuration.Thanks.Best Regards,Ven&nbsp;

vent_altera · Answer

Hi BeJamIn&nbsp;May I know if you have had a chance to review my previous message and try the proposed workaround?&nbsp;&nbsp;Thanks.&nbsp;Best Regards,&nbsp;Ven&nbsp;

bejamin · Answer

Sorry yes I got it to work. I wanted to avoid removing all my connections so I went in to the xml and removed everything that had "core4" in it, and it built fine. It seems IP designer leaves in xml when converting between 4x4 and 1x16.

vent_altera · Answer

Hi BeJamIn&nbsp;Thank you for the updates.Yes, that can be used as a workaround if you prefer not to remove the existing connections.However, the safest path is the approach to remove current MCDMA IP and regenerate a fresh MCDMA IP when changing the mode configuration to ensure all the generated files are all clean and correct.Since the issue has been resolved, I will transition this thread to the community. If you have any new questions, please feel free to open a new thread and the Altera experts will be happy to assist.Thanks.Best Regards,Ven&nbsp;

Forum Discussion

IP components used in the design have conflicting settings. Intel PCIE Ftile MCDMA

4 Replies

Recent Discussions

Marking codes of CY10CL040YF484

Unable to scan JTAG chain, TCK only 2V

Cyclone 10 LP Bitstream Compression Failing

Updated .brd file for Stratix 10 GX dev kit

Agilex 5 D-Series HVIO IOPLL runtime reconfiguration: C0 write succeeds, but output remains 100 MHz