Forum Discussion
New ContributorMarking codes of CY10CL040YF484
please see the attached images and inform whether these devices are faulty or good brought from MOUSER electronics and other vendor.
we are facing issue unable to do JTAG program and if AS mode program done then execution problem.
please suggest what is the problem.
6 Replies
FakhrulA_alteraRegular Contributor
Hi Suvarna,
Thank you for the clarification.
Connecting INIT_DONE, DEV_OE, and DEV_CLRn to GND is acceptable only when these pins are not used and their dedicated functions are disabled in Quartus Device and Pin Options. Please confirm that Enable INIT_DONE output, Enable device-wide output enable (DEV_OE), and Enable device-wide reset (DEV_CLRn) are all turned off, then recompile the SOF/POF files.
If DEV_OE is enabled while held low, all FPGA outputs remain tri-stated. If DEV_CLRn is enabled while held low, all device registers remain reset. Either condition can make the design appear inactive.
Please also note that successful POF programming confirms access to the configuration device, but does not confirm that the FPGA completed configuration and entered user mode. After programming the POF, power-cycle the board and monitor nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0, and nCSO. At the end of successful configuration, nSTATUS and CONF_DONE should both be high.
The absence of the JTAG device ID must be debugged separately. Since the replacement FPGA also gives a JTAG error on the same card, please:- Verify all FPGA power rails directly at the device and confirm ByteBlaster header pin 4 is powered from VCCA.
- Confirm nCE remains low and check TCK, TMS, and TDI directly at the FPGA pins.
- Check TDO continuity from the FPGA pin to the ByteBlaster header.
- Inspect the replaced BGA for open or shorted solder joints, preferably by X-ray, and compare the JTAG-pin continuity with a working card.
Based on the current results, a board connection or assembly issue must be excluded before concluding that the FPGA is defective. If all connections and power rails are verified and the suspect device also fails on a known-good board, please proceed with the RMA via distributor.
Regards,
Fakhrul- FakhrulA_altera
Hi Suvarna,
Thank you for providing the device photographs.
Both devices show the same ordering code, 10CL040YF484I7G, but have different corporate logos and trace/lot markings. These visual differences alone are not sufficient to determine whether a device is faulty or counterfeit.
For devices purchased directly through Mouser’s authorized channel, please retain the invoice and packing-list traceability. For devices from the other vendor, please confirm that the supplier is an authorized distributor and request its certificate of conformance or traceability documents.
The reported JTAG and Active Serial symptoms do not by themselves indicate a device defect. Please perform the following checks:- Run JTAG Auto Detect/read the device ID and provide the complete Quartus Programmer log, Quartus version, download-cable model, and JTAG frequency.
- Verify the FPGA power rails, JTAG signal integrity, Bank 1 VCCIO/reference voltage, MSEL settings, nCE, nCONFIG, nSTATUS, and CONF_DONE.
- For AS operation, verify the programming file and flash-device selection, as well as the nCSO, DCLK, ASDO, and DATA0 connections.
- If possible, test both units on the same known-good board with the same programming file and cable.
If the Mouser units consistently fail while a known-good lot passes under identical conditions, please contact Mouser for RMA support.
Regards,
Fakhrul
suvarnaDear Sir,
Please find the attached schematic
The cards in which JTAG error is coming in that TDO is not coming. in this card CONF_DONE pin always high and NCSO is "LOW" after programming in AS mode and NSTATUS is LOW. NCONFIG once program started its becoming LOWfor some time and then HIGHuntill proram and after Program over in AS mode.
and in working cards NSTATUS during Program LOW and after Program over it is HIGH. CONF_DONE is during Program LOW and after Program over it is HIGH. NCONFIG once program started its becoming LOW for some time and then HIGH untill proram and after Program over in AS mode.
please see my previous mail attached schematic and please see images attached . in working card DEVICE ID is coming and in bad card direct its telling JTAG error.
please see the attached images
VCCIO bank1 voltage is 3.3V only and VREF pins i am using them as i/o pins.
MSEL setting "0010" and nCE grounded with 10k resistor and connected to programmer 6th pin. with same download cable and same program i am loading in to good card and bad card.
TCK freq is 6MHZ waveform attached.
Regards
Suvarna
- FakhrulA_altera
Hi Suvarna,
Thank you for the detailed results.
Because the same cable and programming file work on the good card, while the bad card does not return TDO or a device ID, the failure occurs at the JTAG communication stage before programming.
Please check the following on a failing card:- For a single-device configuration, nCE must remain low and should be connected directly to GND. Please verify the voltage at the FPGA nCE pin during JTAG detection.
- Reduce the JTAG frequency from 6 MHz to 1 MHz, then compare TCK, TMS, TDI, and TDO directly at the FPGA pins on the good and bad cards.
- Check continuity and solder connections for the JTAG and configuration pins, especially TDO, nCE, nSTATUS, and CONF_DONE.
- Confirm that VCCINT, VCCA, and Bank 1 VCCIO remain within specification during JTAG detection.
For AS configuration, nSTATUS remaining low after programming indicates a configuration error. CONF_DONE remaining high throughout programming is also not the expected behavior. Please verify the pull-up and routing of nSTATUS and CONF_DONE, and compare DCLK, DATA0, and nCSO at the FPGA pins against the working card.
If these signals, power rails, and connections are confirmed correct but TDO remains inactive only on the affected devices, the next step is to contact the distributor for RMA or failure analysis.
Regards,
Fakhrul
