Marking codes of CY10CL040YF484

Hi Suvarna,
 

Thank you for the clarification.

Connecting INIT_DONE, DEV_OE, and DEV_CLRn to GND is acceptable only when these pins are not used and their dedicated functions are disabled in Quartus Device and Pin Options. Please confirm that Enable INIT_DONE output, Enable device-wide output enable (DEV_OE), and Enable device-wide reset (DEV_CLRn) are all turned off, then recompile the SOF/POF files.

If DEV_OE is enabled while held low, all FPGA outputs remain tri-stated. If DEV_CLRn is enabled while held low, all device registers remain reset. Either condition can make the design appear inactive.

Please also note that successful POF programming confirms access to the configuration device, but does not confirm that the FPGA completed configuration and entered user mode. After programming the POF, power-cycle the board and monitor nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0, and nCSO. At the end of successful configuration, nSTATUS and CONF_DONE should both be high.

The absence of the JTAG device ID must be debugged separately. Since the replacement FPGA also gives a JTAG error on the same card, please:

• Verify all FPGA power rails directly at the device and confirm ByteBlaster header pin 4 is powered from VCCA.
• Confirm nCE remains low and check TCK, TMS, and TDI directly at the FPGA pins.
• Check TDO continuity from the FPGA pin to the ByteBlaster header.
• Inspect the replaced BGA for open or shorted solder joints, preferably by X-ray, and compare the JTAG-pin continuity with a working card.

Based on the current results, a board connection or assembly issue must be excluded before concluding that the FPGA is defective. If all connections and power rails are verified and the suspect device also fails on a known-good board, please proceed with the RMA via distributor.

Regards,
Fakhrul