Agilex 5 D-Series HVIO IOPLL runtime reconfiguration: C0 write succeeds, but output remains 100 MHz

I am trying to change an Agilex 5 D-Series HVIO IOPLL output from 100 MHz to 50 MHz at runtime through the core_avl reconfiguration interface.

The register transactions appear to work correctly: C0 at 0x05C can be written and read back successfully, and Signal Tap confirms that the reset (0x080), recalibration enable (0x048), and recalibration request (0x088) commands all reach the IOPLL interface with the expected data.

However, the physical output clock still remains at 100 MHz, and locked stays high throughout the procedure.

My main problem is that I cannot determine whether the new C0 divider is actually being applied to the active PLL, or whether the recalibration cycle is not really starting/completing.

 Problem: Runtime writes to the Agilex 5 HVIO IOPLL reconfiguration registers succeed, including C0 write/readback and the documented reset/recalibration sequence, but the output frequency does not change from 100 MHz to 50 MHz. locked remains high, so I cannot tell whether recalibration actually starts or whether the new C0 value is applied to the active divider.

 Environment:

Device: Agilex 5 A5ED013BB32AE4S

Board: Terasic DE25-Standard Rev. 

Quartus Prime Pro: 26.1

Reference clock: 50 MHz

Initial IOPLL output: 100 MHz

Target runtime output: 50 MHz

What I have verified

HVIO dynamic reconfiguration is enabled.

core_avl_clk is running at 50 MHz

Register access at 0x010[0] is enabled.

Calibration status bits 0x058[7] and [21] are cleared according to the Agilex 5 D-Series 25.1.1 guide.

C0 register address is 0x05C.

C0 can be written and read back correctly.

For the 50 MHz test, I use:

high_count = 32 low_count = 32 bypass = 0 odd = 0

which gives:

 C0 = 0x10000C20

 The hardware readback after writing C0 is also 0x10000C20.

 Signal Tap confirms that the following writes reach the actual IOPLL core_avl interface:

 0x080 = 0x00000004 // PLL reset 0x048 = 0x00004000 // recalibration enable 0x088 = 0x00000800 // recalibration request.

 The 0x080[2] reset pulse is longer than 10 ns, and there are no bridge errors, rejected transactions, or timeouts.

 I also compared known-good static 100 MHz and 50 MHz Quartus-generated configurations. The main implemented difference is:

 Static 100 MHz: C0 divide = 32 high/low = 16/16 Static 50 MHz: C0 divide = 64 high/low = 32/32

 M, N, VCO, compensation mode, phase, and the other relevant PLL parameters remain unchanged.

 Observed result:

After the complete runtime sequence:

 C0 final readback = 0x10000C20 locked = 1 output clock = still 100 MHz.

So the register value is retained, but the active output divider does not appear to change. 

Questions:

If locked is already high before asserting 0x088[11], how can I confirm that a new recalibration cycle actually starts and completes?Does successful C0 readback at 0x05C mean the new divider value is ready to be applied to the active PLL, or is another condition required?Is there any additional documented step after 0x080[2], 0x048[14], and 0x088[11] before the new C0 divider becomes active?Is the Agilex 5 HVIO IOPLL runtime reconfiguration example #16029156620 available?

I can provide Signal Tap captures for the 0x080, 0x048, and 0x088 transactions, as well as the complete UART register log if needed.

Thanks.