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jiayao
New Contributor
New ContributorAgilex 5 D-Series HVIO IOPLL runtime reconfiguration: C0 write succeeds, but output remains 100 MHz
I am trying to change an Agilex 5 D-Series HVIO IOPLL output from 100 MHz to 50 MHz at runtime through the core_avl reconfiguration interface. The register transactions appear to work correctly: ...
AqidAyman_Altera
Regular Contributor
Regular ContributorHello,
The locked signal remaining high while 0x080[2] is asserted strongly indicates the active-PLL reset register is not being accessed. Since this is a production device, HVIO core_avl interface requires word addressing. Although the register transactions complete, the displayed addresses are the documented byte offsets.
Please refer to the following KDB and repeat the sequence using word addresses:
Why does Agilex® 5 FPGA and Agilex® FPGA 3 HVIO PLL fail to lock after reconfiguration? | Altera Community - 354904
If the output still stays at 100 MHz after confirming word addresses at the physical HVIO interface, please provide the stp capture and the transaction log for further checking.
Regards,
Aqid
