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BeJamIn's avatar
BeJamIn
Icon for New Contributor rankNew Contributor
2 months ago

IP components used in the design have conflicting settings. Intel PCIE Ftile MCDMA

I generated a 4x4 PCIE MCDMA using the ip designer using quartus 25.3.0.109 from the example design from https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-a...
Programmable Logic Device
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 months ago

Hi BeJamIn

Thank you for reaching out to us.

Could you please regenerate the MCDMA IP from scratch using the 1x16 IP mode configuration? Instead of modifying the existing 4x4 MCDMA IP, please create a new MCDMA IP instance in Platform Designer and select 1x16 during the initial IP configuration. The reason for this recommendation is that changing the IP mode from 4x4 to 1x16 through the GUI may not fully reset the internal parameters associated with the unused sub-cores, which could lead to unexpected behavior.

Please let me know whether the issue persists after regenerating the fresh IP for 1x16 mode configuration.

Thanks.
Best Regards,
Ven