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BeJamIn's avatar
BeJamIn
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14 hours ago

IP components used in the design have conflicting settings. Intel PCIE Ftile MCDMA

I generated a 4x4 PCIE MCDMA using the ip designer using quartus 25.3.0.109 from the example design from https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/pcie_rp/ug-pcie_rp-a...