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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Suggestion of carry chain type TDC of Cyclone 10 GX FPGA chips

Hello Guys,

I read one post here, which requested the way to design carry chain style TDC based on Agilex 9 chips. 

Here is that post linkcarry chain tdc | Altera Community - 351924

Kenney answer that post and give some recommendations about it. Now I have similar questions about carry chain TDC by using ALTERA's Cyclone 10 GX. Is that wire LUT delay lines in Cyclone 10 Gx devices?

Core Logic
Programmable Logic Device

6 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    3 months ago

    Hi,

     

    This is Kenny here, if you are using cyclone 10 GX, the TDC implementation would be more direct.

     

    Can you check your email for more info?

     

    Thanks,

    • MinzhiWang's avatar
      MinzhiWang
      Icon for Occasional Contributor rankOccasional Contributor
      3 months ago

      Hi Kenny, 

      Do you mean that you sent some materials to my email? But I didn't get any information from you.  My e-mail only received some notices sent by Altera community. I think they are sent by community automatically.

       

      BTW, I also receive you message here, my altera community account message box.

    • MohammadShabih_ENG's avatar
      MohammadShabih_ENG
      Icon for New Contributor rankNew Contributor
      2 months ago

      Hi Kenny, could you explain the TDC implementation on the cyclone 10 LP? My particular use case requires accessing each carry-out bit in the carry chain for processing.  
      Thank you, I would appreciate any help. 

      • KennyT_altera's avatar
        KennyT_altera
        Icon for Super Contributor rankSuper Contributor
        2 months ago

        Hi Mohammed Shabih,

         

        Kindly check your inbox for message.

         

        Thanks,