Forum Discussion
New ContributorLeakage Current in MAX 10 Bank 1A (ADC Bank)
Device：10M08DCF256I7G
We have connected the following voltage divider circuit to each of Bank 1A and Bank 8 of the MAX 10 device.
12 V → 10 kΩ / 3.6 kΩ voltage divider → MAX 10 input (typical voltage: 3.18 V)
The measured voltages at each bank are as follows:
Bank 8: 3.17 V
Bank 1A: 3.06 V
The voltage at Bank 1A is lower than that at Bank 8. We checked the 12 V input voltage and resistor tolerances, but found no deviations large enough to account for this difference.
We also found the following statements in the datasheet:
//////////
The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).
10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed when the diode is on.
Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable to all Intel MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.
//////////
Could you please confirm whether it is reasonable to conclude that this phenomenon is caused by leakage current specific to Bank 1A (the ADC bank)?
1 Reply
ai_responderCommunity Manager
Yes, that conclusion is entirely reasonable. Here's the supporting analysis.
What the datasheet says about Bank 1A ADC pin leakage
Standard I/O pins carry a leakage spec of only ±10 µA for both input pin leakage current (II, VI = 0 V to VCCIOMAX) and tristated I/O pin leakage current (IOZ, VO = 0 V to VCCIOMAX). MAX 10 FPGA Device Datasheet However, the ADC I/O pins in Bank 1A carry a separate, much higher leakage spec: input channel leakage up to a maximum of 1.8 mA, and this leakage occurs whether the ADC IP core is enabled or disabled. MAX 10 FPGA Device Datasheet
Does the math support your observation?
Your 10 kΩ / 3.6 kΩ voltage divider presents a Thévenin source resistance of approximately:
10 kΩ ∥ 3.6 kΩ ≈ 2.65 kΩ
The observed voltage drop on Bank 1A relative to Bank 8 is:
3.17 V − 3.06 V = 0.11 V
The implied leakage current drawing that voltage down through the divider's source impedance is:
0.11 V ÷ 2.65 kΩ ≈ 41.5 µA
This is well above the ±10 µA normal I/O leakage spec (consistent with Bank 8 showing negligible drop), and well within the documented 1.8 mA ADC I/O pin leakage ceiling for Bank 1A. The numbers are fully consistent with ADC-specific pin leakage on Bank 1A pulling additional current from your high-impedance divider.
Root cause summary
The 110 mV deficit on Bank 1A is the expected consequence of routing a high-impedance voltage divider (Thévenin ~2.65 kΩ) into ADC analog input pins whose leakage current is documented to reach the milliamp range. The standard 10 µA I/O leakage limit applies only when the internal clamping diode is off MAX 10 FPGA Device Datasheet — the ADC pin leakage mechanism is separate and inherently higher.
Practical recommendation
If you need accurate voltage measurement at the ADC input, lower the source impedance of your voltage divider significantly (to tens of ohms or low hundreds of ohms at most), so that ADC pin leakage current does not create a meaningful IR drop before the device pin. The crosstalk requirement for analog-to-digital signal is −100 dB up to 2 GHz MAX 10 FPGA Signal Integrity Design Guidelines , so routing discipline matters too, but the immediate issue here is source-impedance interaction with the documented ADC pin leakage.
Note: To continue using AI Responder, please start your next inquiry with ai_responderDisclaimer (Beta): The AI Responder is currently provided as a beta feature. AI-generated responses may contain errors or omissions. Please verify technical guidance with official Altera documentation before implementation.
Thank you very much.
