Leakage Current in MAX 10 Bank 1A (ADC Bank)

Yes, that conclusion is entirely reasonable. Here's the supporting analysis.

What the datasheet says about Bank 1A ADC pin leakage

Standard I/O pins carry a leakage spec of only ±10 µA for both input pin leakage current (II, VI = 0 V to VCCIO_MAX) and tristated I/O pin leakage current (IOZ, VO = 0 V to VCCIO_MAX). MAX 10 FPGA Device Datasheet However, the ADC I/O pins in Bank 1A carry a separate, much higher leakage spec: input channel leakage up to a maximum of 1.8 mA, and this leakage occurs whether the ADC IP core is enabled or disabled. MAX 10 FPGA Device Datasheet

Does the math support your observation?

Your 10 kΩ / 3.6 kΩ voltage divider presents a Thévenin source resistance of approximately:

10 kΩ ∥ 3.6 kΩ ≈ 2.65 kΩ

The observed voltage drop on Bank 1A relative to Bank 8 is:

3.17 V − 3.06 V = 0.11 V

The implied leakage current drawing that voltage down through the divider's source impedance is:

0.11 V ÷ 2.65 kΩ ≈ 41.5 µA

This is well above the ±10 µA normal I/O leakage spec (consistent with Bank 8 showing negligible drop), and well within the documented 1.8 mA ADC I/O pin leakage ceiling for Bank 1A. The numbers are fully consistent with ADC-specific pin leakage on Bank 1A pulling additional current from your high-impedance divider.

Root cause summary

The 110 mV deficit on Bank 1A is the expected consequence of routing a high-impedance voltage divider (Thévenin ~2.65 kΩ) into ADC analog input pins whose leakage current is documented to reach the milliamp range. The standard 10 µA I/O leakage limit applies only when the internal clamping diode is off MAX 10 FPGA Device Datasheet — the ADC pin leakage mechanism is separate and inherently higher.

Practical recommendation

If you need accurate voltage measurement at the ADC input, lower the source impedance of your voltage divider significantly (to tens of ohms or low hundreds of ohms at most), so that ADC pin leakage current does not create a meaningful IR drop before the device pin. The crosstalk requirement for analog-to-digital signal is −100 dB up to 2 GHz MAX 10 FPGA Signal Integrity Design Guidelines , so routing discipline matters too, but the immediate issue here is source-impedance interaction with the documented ADC pin leakage.

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