s002wjhwen
New Contributor
New Contributorcarry chain tdc
is there a primitive on altera (similar to xilinx carry4) i can use to do carry chain tdc? i need resolution around 30ps ish. any example code? thanks
Forum Discussion
7 Replies
s002wjhwenor other ways to do 30ps ish resolution?
KennyT_alteraSuper Contributor
Do you have any update for the above?
- KennyT_altera
Do you have any update for the above?
FvMHi,
tons of papers about TDC implementation, but less coding details. Searching for references to specific FPGA families helps. Here a free IEEE Access paper
N. F. Charlot, D. J. Gauthier and A. Pomerance, "High-Resolution Waveform Capture Device on a Cyclone-V FPGA"
IEEE Xplore Full-Text PDF:
Regards
Frank- KennyT_altera
what device you are targeting? as different device will have different approaches.
- s002wjhwen
i'm using agilex 9, i see article and papers, but not sure which primitive to use for agilex 9
- KennyT_altera
Thank you for your inquiry regarding carry chain TDC implementation on Altera Agilex 9 FPGAs and achieving ~30ps resolution.
Carry Chain TDC on Agilex 9
Altera FPGAs do not provide a direct equivalent to the Xilinx CARRY4 primitive. However, carry chain logic can be inferred by implementing arithmetic structures (such as adders) in your HDL. The Quartus compiler maps these structures to the device’s carry chain resources, enabling TDC applications.
Example code and WYSIWYG usage:
You can use Altera's low-level WYSIWYG logic modules (e.g., tennm_logic_module) to directly instantiate and control carry chain resources. Example designs and code snippets are available(Check your email) for experimentation, and manual placement/routing in Quartus Chip Planner is recommended for optimal results.Important Caveats
Based on our experience:
- Carry-based predictable delay methods are less effective on newer FPGAs (like Agilex 9) compared to older devices. Architectural changes, such as carry lookahead logic, introduce significant non-uniformity in delay steps.
- Absolute delays are decreasing in modern chips, making tap-to-tap delay smaller and harder to calibrate precisely.
- Variation in delay is increasing—bin widths are not uniform, and per-bin calibration is often necessary. Linearity and monotonicity cannot be guaranteed across the chain.
- Resolution of ~30ps is possible, but achieving consistent and predictable results is more challenging.
Recommended Alternative
For more uniform and controllable delays, we recommend experimenting with wire LUT delay lines instead of relying solely on carry chains. Wire LUTs, combined with manual placement and routing, have proven to deliver more consistent results on Agilex devices.
Measurement methodology:
Linearity is typically measured using a ring oscillator or periodic signal, sampled through your delay line. A histogram of hits per bin allows you to calculate propagation delay differences and calibrate accordingly.
