Forum Discussion
New ContributorImplementation of lower data rate.
Hi, I would like to know about implementation of lower data rates (100 - 200Mbps) in cyclone 5 GX and cyclone 10 GX FPGA's. please provide the support by providing the architecture.
2 Replies
FvMSuper Contributor
Hi Varun,
guess you are asking about operating transceivers at low data rates? Cyclone 10 GX minimal transceivers speed is 1 Gbps, CV GX 614 Mbps. As mentioned in 10 GX transceiver PHY user guide, lower data rates can be achieved by oversampling. The questioned data rates can be implemented directly with LVDS IO, what's the reason to use tranceiver channels?
Regards
Frank- Ash_R_Altera
Regular Contributor
Hi Varun,
As Frank mentioned, you can use LVDS IOs in the FPGAs to interface for data rates between 100-200 Mbps. You may use following user guides to do so.
https://docs.altera.com/r/docs/683520/current
https://docs.altera.com/r/docs/683062/current
Regards
