Forum Discussion
Varun_N_C
New Contributor
New ContributorImplementation of lower data rate.
Hi, I would like to know about implementation of lower data rates (100 - 200Mbps) in cyclone 5 GX and cyclone 10 GX FPGA's. please provide the support by providing the architecture.
Ash_R_Altera
Regular Contributor
Regular ContributorHi Varun,
As Frank mentioned, you can use LVDS IOs in the FPGAs to interface for data rates between 100-200 Mbps. You may use following user guides to do so.
https://docs.altera.com/r/docs/683520/current
https://docs.altera.com/r/docs/683062/current
Regards
