New ContributorHi all,
I have Quartus 25.2 and I'm looking to run some tests in loopback mode without having any physical hardware connected. I have Reflexv2 FPGA Card. Can you guide me which IP from quartus should i choose to run loopback for testing purposes? I want only to run internal loopback, without card connection.
Best Regards,
Przemyslaw Pajak
Regular ContributorHi,
May I know the intent of your test. Are you planning to test only the transceivers or any specific protocol?
If it is only transceivers, then you may use the internal serial loopback within the XCVR buffer. It loops back the Tx serial data to the Rx serial line.
You may generate the example design from the F-tile PMA/FEC Direct PHY IP https://docs.altera.com/r/docs/683872/25.3/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/example-design-generation and modify according to your board pinouts. Use the register settings to enable internal serial loopback to test it out.
Alternatively, you can also use the transceiver toolkit to enable internal loopbacks. For this, you will have to enable few options in the IP GUI of the generated example design and make changes to the wrapper file as mentioned in the following section of the user guide. https://docs.altera.com/r/docs/683872/25.3/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/using-debug-endpoint-interface-within-the-f-tile-pma/fec-direct-phy-ip
Hope this helps.
Regards
Regular ContributorI’d appreciate it if you could confirm whether the issue is now resolved.
New ContributorHi thank you for quick response,
My intent is to test only internal loopback, I want to drive single frame on Tx MAC AVST protocol and receive single frame on Rx AVST protocol. I do not want to use external loopback. I have performed test with my Reflexv2 board according to F-Tile Ethernet Intel FPGA Hard IP 23.4 Design Example User Guide. I successfully generated project and ported it to Reflexv2. However when I performed run test script to test internal loopback I had a problem. Test has returned that pcs ready signal has not established.
I slightly modified this project, added my reset sequence, and performed successfully loopback, but I needed to:
Enable PCS TX RX Loopback inside IP MAC. Connect qsfp dd cable that is split for 2x qsfp into E810 card.
Then I have observed that pcs ready has been established. I have received TX Ready on AVST and I was able to send and receive single frame on RX AVST interface. And here is my concern. Is that possible to do it without connection to external card? Otherwise pcs ready is low and I do not see TX Ready signal on AVST interface.
Best Regards, Przemyslaw
Regular ContributorHi,
Not sure which example design have you selected. Can you point the one in the UG: https://docs.altera.com/r/docs/683804/current
We can assure you that all the example designs are well tested on Altera devkits and/or simulation.
The basic steps to run the designs on hardware are to call the right script.
source main_<Ethernet_rate>.tcl
set_jtag<number_of appropriate_JTAG_master>
Regards
Regular ContributorHi,
Any further comment on the topic? Wanted to understand which design example you have chosen.
Regards
New ContributorHi,
It seems that i have resolved problem. For use case i needed (check loopback on Reflexv2 card).
Finally i have used F-Tile Mac IP for quartus 23.4 (i am not sure if quartus support Reflexv2 in newer version), and generated example design, with below parameters. Then i have changed constrains for Reflexv2 card (initially it was left unassigned). Then i generated my custom module for driving reset sequence (same way like it was done in example TB). Finally i have selected loopback in ip for MAC PCS_TX_RX parameter. In next step i have connected Card to E810 Network adapter and finally i have observed rx_lanes_stable and pcs_ready signals. After that i was able to send and receive frame in AVST TX/RX interface.
So to conclude i have performed loopback in Reflexv2 card. I think we may close this topic.
Best Regards,
Przemyslaw
