Bidirectional differential port on MAX10
I want to implement a bidirectional differential port on a MAX10 10M02SCU324C8G I first tried to do it on my own and then tried to do it with the GPIO Lite IP too. At the end of the day I get the same error: Error (176202): The differential I/O standard Differential 2.5-V SSTL Class I cannot be used on the pin RC_A[0], because the specified pin uses a tri-stated output buffer. Is it only possible to have either a dedicated input or output differential port? Why is it even letting me configure the IP as a bidirectional differential IO? Or am I missing something when it comes to pin configuration?
QSPI DDR Interface with Cyclone10LP: Maximum frequency
Hello, We are planning to implement a QSPI interface between Altera Cyclone10LP (10CL025YU256A7G) and a microcontroller iMXRT1180. The microcontroller is capable of a maximum frequency of 166 MHz (which would mean 332MHz DDR) on the QSPI interface. We want to know which would be the maximum frequency we are able to achieve on the FPGA for this interface. We have this information extracted from the datasheet: "I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load." Does this mean the pins will not be able to accept data changing at a rate faster than 200 MHz or will it be possible to have something like a fHSCLK of 200 MHz (which would mean double device operation in Mbps) as we can see in Table 24 (example for RSDS Transmitter) on the datasheet? Are there any special pins on the FPGA which we can use to achieve maximum potential on this interface? Or any strategies like using IDDR/ODDR modules that could help? Any suggestions are welcome. Thank you!LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve
Hi Team, I am facing a pin assignment issue with LVDS TX and RX IP in Quartus Prime. I have tried all the suggestions provided earlier (bank selection, I/O standard, refclk, PLL connections, and pin constraints), but I am still encountering pin assignment errors during compilation. Details: - Device: AGIB022R31A2I2VB - Tool: Quartus Prime 25.1.1 - LVDS IP: TX and RX - Mode: External pll mode in both TX and RX - Issue: Pin assignment errors related to LVDS TX/RX signals I have verified: - Correct I/O banks and VCCIO - Differential pair placement - Dedicated reference clock usage - PLL lock status Despite this, the issue persists. I have attached all relevant files: - .qsf If possible, could someone please: 1. Review the attached files and point out what might be wrong, OR 2. Share a small working reference project for LVDS TX/RX pin assignment I am also open to discussing this over a call if needed, as it may be easier to debug. Any guidance would be appreciated. Thanks & Regards, Hari
Agilex 7 F/I Series True Differential Input Termination
Hi, The Agilex F/I Series GPIO User Guide indicates that if using AC coupling for the true differential inputs you should add external voltage bias circuitry and has no examples of AC coupling without also externally biasing the inputs as shown in snippet below. I would like to confirm whether the Agilex 7 F/I series parts have internal voltage biasing such that if AC coupling, external biasing resistors would not be needed so long as VID (max 600mV, so 1200mV differential pk-pk max) is being met? The IBIS model for the part shows a consistent voltage bias for the inputs that is within the VICM range listed in the Agilex 7 F/I series datasheet (see snippet below) which implies the external biasing is not needed. And the AGILEX FM86/FM76 DEVELOPMENT KIT has some differential inputs that are AC coupled with no external biasing.Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hello, I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it. Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. The A692 Power Sequencing Considerations app note states the below: So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. The Agilex 7 General-Purpose I/O User Guide states the following: Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS. Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. I don't see any mention of similar constraint for Transceiver I/O. The Agilex 7 Power Management User Guide states the following: Again, I see all I/O other than Transceiver I/O mentioned. Thanks!
PCIe not working (no enumeration) Agilex™ 5 FPGA E-Series 065B Modular Development Kit
Hello, I recently got this dev board, and I was trying to load the PCIe example design up on the board however it seems that it is not working, as it fails to enumerate! I followed the instructions on the PDF guide, and I also have my switches set correctly, however it is not working unfortunately! I assume that its an issue with the MAX 10 file, however the only other one I found on the forum is incompatible with my board! I also have the switches set correctly (SW13.1 ON), but any idea or thing helps! Thanks in advance for the help!
