Cyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, Brian
Pin package delay for Agilex 5
Hello, For a new PCB design using Agilex 5 (package B32A, 32x32mm 1591 pin BGA), I need the Agilex™ 5 Device Package Net Length Report , however the link is down and I can't find the information anywhere. We need it to equalize routing length on LPDDR4 Thank you in advance Guy
HDMI example design errors with Agilex 7
Hello, I generated the HDMI example design for the Agilex 7 devkit and it compiled and worked fine. But when I ported it to my platform and remapped it to the nwe pins, I get these errors (for evenry RX lane and every TX lane): Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_ref_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_ref_hz) > 99999899 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == TRUE || (gdr.z1577b.u_ux_quad_3.flux_top.ux0_rx_tuning_hint -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.rx_tuning_hint) == UX0_RX_TUNING_HINT_HDMI Error(21843): (gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_f_out_hz -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_0|rx_phy_12g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx.cdr_f_out_hz) == 0 || gdr.z1577b.u_ux_quad_3.flux_top.ux0_cdr_powerdown_mode == FALSE Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): gdr.z1577b.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577b.u_ux_quad_3.powerdown_mode == FALSE Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ux_rx[3] -> hdmi21_i|u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_30|rx_phy_3p500g|dphy_hip_inst|persystem[3].perxcvr[0].fgt.rx_ux.x_bb_f_ux_rx ... Can you please clarify what the issue is? On my new platform, I am using Bank 12A Quad 3 (TX and RX) and for reference clocks fgt_12a_refclk_ch3 and fgt_12a_refclk_ch4. Thanks
Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?
I was hoping to use LVDS serdes IP to implement acquisition system of 12 -bit ADC data using 2-wire LVDS: However, this is not possible if only serialization factors of 4 and 8 are supported. Is there a workaround or will this be supported in the future?MAX10 ADC Problem BANK 1A 1B 8
I have used a max10 chip and quartus 18 for the project. I have encourtered with ADC critical warning (16248). How can I solve this problem. For Bank 1B I can move the pins to other locations but the BANK 8 is vague because it lets some of the pins can be used. However it does not say which pins to be used properly. I have researched about this topic and I have found this source. https://docs.altera.com/r/docs/683751/25.1/max-10-general-purpose-i/o-user-guide/guidelines-analog-to-digital-converter-i/o-restriction Is there other resources that could explain this problem and the solution? what should I do?
Request for Cyclone V Pinout File Information
I would like to download the Cyclone V pinout file (Excel format) from the Altera website; however, an error occurs and I am unable to download the file. https://www.altera.com/design/devices/resources/pinouts Could you please advise on how to resolve this issue and inform me of any alternative methods to obtain the Cyclone V pinout file?
Question for LPDDR5 power sharing guideline
Hi altera, In the Agilex 7 M-series Pin connection guideline document, I can find guidline for Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using LPDDR5. 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 • Agilex™ 7 Device Family Pin Connection Guidelines M-Series • Altera Documentation and Resources Center When applying LPDDR5 component to the Agilex 7 M-series, which section should I refer to regarding the power sharing guideline? Thanks.Does the Agilex7 M-series support LPDDR5X component?
Hi Altera, I want to use a LPDDR5X component on Agilex 7 M-series. Does the Agilex7 M-series support LPDDR5X components? The LPDDR5X part number is MT62F1G32D2DS-020 WT:D Functional Technology Supply Voltage Useable Density Configuration Width Data Rate Clock Speed MT62F1G32D2DS-020 WT:D LPDDR5X 1.05 VOLTS 32Gb X32 9600MTPS 4800 Thanks.
Bidirectional differential port on MAX10
I want to implement a bidirectional differential port on a MAX10 10M02SCU324C8G I first tried to do it on my own and then tried to do it with the GPIO Lite IP too. At the end of the day I get the same error: Error (176202): The differential I/O standard Differential 2.5-V SSTL Class I cannot be used on the pin RC_A[0], because the specified pin uses a tri-stated output buffer. Is it only possible to have either a dedicated input or output differential port? Why is it even letting me configure the IP as a bidirectional differential IO? Or am I missing something when it comes to pin configuration?
