generic io

235 Topics

Regarding the Footprint creation of AGFB022R24C2E2V
Hi For the AGFB022R24C2E2V The package drawing specifies a solder resist opening of Ø0.50 ± 0.02 mm, but it does not specify the recommended PCB pad diameter. Could you please provide the recommended PCB land pattern, including the copper pad diameter and whether the pads should be solder mask defined (SMD) or non-solder mask defined (NSMD)? Addition please provide the Allegro footprint for AGFB022R24C2E2V
Roshan
1 hour ago Place FPGA Device
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Global Clock & Regional clock inputs in Agilex M FPGA
Hi, Kindly answer the following queries related to reference clocks in F-Tile of Agilex M FPGA. Why F-Tile in Agilex M series FPGA needs four Global Clock input signals & Four regional clock inputs signals ? Why multiple clock inputs of Global clocks and Regional clocks are provided in F-Tile of Agilex M FPGA? Can I drive only one global clock input with 156.25MHz & and use Eight FGT tansceivers (in two quads) in F-Tile to get 400GE ? Or I have to drive at least two global input clocks ? When do we need to drive regional clock inputs ? When do I need to drive global clock inputs ? In reference design(Agilex M GPGA 3xF-Tile 1xR-Tile based), two clocks of different values(390.625MH, 156.25MHz) are driving the reference clock inputs. Why ? Regards, Thulasi
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Thulasi
1 day ago Place FPGA Device
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URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
SiddeshChavan
1 day ago Place FPGA Device
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Error (209014): CONF_DONE pin failed to go high in device 1.
I want to flash a simple led blink code bitstream file in Cyclone V E Dev kit using USB blaster. When I am trying to flash using USB blaster I am getting below error: Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. I tried to configure the DPI switch below combination: DPI SW1.1 =ON, 1.2 = ON, 1.3=ON, 1.4=ON DPI SW2.1=OFF,2.2=ON,2.3=OFF,2.4=OFF & same switch i tried DPI SW2.1=ON,2.2=ON,2.3=OFF,2.4=OFF DPI SW4.1=ON,4.2=OFF,4.3=OFF,4.4=OFF When I am opening programmer and hardware setup USB Blaster is coming and then I am performing auto detect and it is showing 3 options: 5CEBA7 5CEFA7 5CEFA7ES I choose 5CEFA7 and then change the files and choose configure and the start. But after 32% it is showing failed and i am getting the error message. Can anyone plese suggest do I set the DPI switch correctly or shall I miss anything.
Sameer-sahu
4 days ago Place FPGA Device
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Arria 10 QSPI controller hangs after U-Boot shell while SPL boots successfully
Hello, I am debugging a QSPI issue on two custom Arria 10 SoC boards. The boards are not the same FPGA package, but they are based on the same project. The only difference between the builds is the generated HPS handoff. On both boards: SPL boots successfully from QSPI flash. U-Boot FIT image is loaded successfully. U-Boot reaches the shell. During boot, U-Boot tries to read the environment from QSPI. On the working board: sf probe works. saveenv works. I can access the QSPI controller registers after U-Boot shell. Reading the QSPI module ID register works. On the failing board: SPL still boots correctly from the same QSPI flash flow. U-Boot also reaches the shell. The environment area is empty because saveenv cannot be executed successfully. Any command that accesses the flash, such as sf probe, hangs. Eventually the watchdog resets the board. After the U-Boot shell is up, I also cannot read the QSPI module ID register. The QSPI register base address from the address map is: i_qspi_qspiregs base: 0xFF809000 end: 0xFF8C07FF The module ID register is: offset: 0xFC expected value: 0x1001 So I am trying to read: 0xFF809000 + 0xFC = 0xFF8090FC On the working board this read succeeds. On the failing board this read hangs / causes the system to stop, and then the watchdog resets the board. I also checked the reset manager from U-Boot: md.l 0xFFD05014 4 The first value was: 0x00000000 So it does not look like the QSPI controller is held in reset. Additional observations from logic analyzer: JEDEC ID command 0x9F is sent correctly. The flash responds with a valid ID, for example: 0x20 0xBB 0x22 Later U-Boot sends a 4-byte read command: 0x13 0x00 0x20 0x00 0x00 The flash returns only 0xFF. I also tried compiling SPL and U-Boot separately for the failing board, instead of using the full project build, but the result was exactly the same. My questions are: What can cause the Cadence QSPI controller to work correctly during SPL and early U-Boot boot, but stop responding after reaching the U-Boot shell? Can a wrong HPS handoff, clock configuration, pinmux, bridge/firewall setting, or reset configuration cause this behavior only after U-Boot relocation/shell? Which Arria 10 registers should I check to verify that the QSPI controller clock, reset, and access permissions are still valid after U-Boot shell? Why would reading the QSPI controller module ID register hang on one board but work on another, while both can still boot SPL and U-Boot from QSPI? Any suggestions on what to check next would be appreciated. Thanks.
Solved
LironAvrhmov
12 days ago Place FPGA Device
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Global Clock & Regional clock inputs in Agilex M FPGA
Hi, Kindly answer the following query related to USB PHY connection to MAX10 in Agilex I series FPGA design. In the reference design, why USB phy is connected to BMC(MAX10) in PCIe based card based on Agilex I FPGA design. What can be done using USB interface in the the design. Regards, Thulasi
Thulasi
12 days ago Place FPGA Device
54Views
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Pin-Out File request A5EC028AB32AE3V (Agilex 5 E-Series, B32A package) [for Altera Employees Only]
Hi Altera team, I'm currently working on a new board design based on the Agilex 5 E-Series, specifically the A5EC028AB32AE3V in the B32A (32 × 32 mm VPBGA) package, using Quartus Prime Pro Edition. Quartus already recognizes this part number and lets me place pin assignments without any issue, but I couldn't find the matching Device Pin-Out File anywhere on the official pinouts page: 🔗 https://www.altera.com/design/devices/resources/pinouts Without that file, it's really hard to move forward, since I still need to finalize the PCB symbol, map the banks to their supplies correctly, and lock down the land pattern for the B32A package. Could someone from Altera kindly help me with the following? The official Pin-Out File (.pdf or .txt) for A5EC028AB32AE3V. The B32A package drawing along with the recommended PCB land pattern. A quick confirmation that the Agilex 5 Pin Connection Guidelines fully apply to this specific SKU. Just to clarify, we don't currently have active APS access on our side, which is why I was directed to reach out through the forum. Since this involves device-specific information, I'd prefer to continue the conversation privately. If an Altera AE could reply via private message on this thread, that would be much appreciated.
Omer_T
21 days ago Place FPGA Device
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Agilex 5 LVDS reciver with custom pins
Hi all, We are working on an Agilex 5 project based on Eagleboard with the device A5ED065BB32AE4SR0. Our aim is to use the Cruvi connectors on the board, so we have to configure our pinning according to the board connections. Therefore, we need to use custom pinning for our LVDS receivers. We have been able to successfully set 4 LVDS lanes in I/O Bank 3B_B lane 1 and the reference clock in a differential pair of the same sub bank but in lane 2. Then we tried to set a receiver with 8 lanes using the same 4 differential pairs from I/O Bank 3B_B lane1 and 4 available differential pairs from I/O Bank 3B_B lane2. Like in the following pin planner screenshoot The parameter editor looks like follows, no errors are shown on core generator Once the LVDS receiver is regenerated and new pins assigned, we got the following error related to the 4 new lanes added: Error(14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error(175019): Illegal constraint of I/O pad to the location PIN_K65 Info(14596): Information about the failing component(s): Info(175028): The I/O pad name(s): Sensor2_Data_n[4] Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected) Info(175029): PIN_K65. Already placed at this location: I/O pad Sensor2_Data_p[4](n) Error(175019): Illegal constraint of I/O pad to the location PIN_K74 Info(14596): Information about the failing component(s): Info(175028): The I/O pad name(s): Sensor2_Data_n[5] Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected) Info(175029): PIN_K74. Already placed at this location: I/O pad Sensor2_Data_p[5](n) Error(175019): Illegal constraint of I/O pad to the location PIN_T74 Info(14596): Information about the failing component(s): Info(175028): The I/O pad name(s): Sensor2_Data_n[6] Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected) Info(175029): PIN_T74. Already placed at this location: I/O pad Sensor2_Data_p[6](n) Error(175019): Illegal constraint of I/O pad to the location PIN_T77 Info(14596): Information about the failing component(s): Info(175028): The I/O pad name(s): Sensor2_Data_n[7] Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected) Info(175029): PIN_T77. Already placed at this location: I/O pad Sensor2_Data_p[7](n) It seems like the fitter tries to create and assign new complementary ping where there are already assigned ones. Could you help us with this? Best regards
K_ED_RD1
29 days ago Place FPGA Device
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about cyclone 10gx transceiver
Hi, recently I am trying to debug cyclone 10 gx transceivers, and the settings are as the figures above. After reseting, I first send 32'h12345678 as the control world, and set tx_control[1:0] = 2'b10. During this time, in my logic I using rx_bitslip to slip the bits until rx_parallel_data is equal to 32'h12345678. After that, I continually send incremental counter value through transmitter with tx_control[1:0] = 2'b01, but the receiver gets rx_control[1:0] equal to 1, 2, 3, changing all the time, which is shown as following figure. So, did I set parameters wrongly? Or how can l solve it? Thank you.
SiWu
1 month ago Place FPGA Device
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Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi, I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me. Thank you
chandu_12867
1 month ago Place FPGA Device
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6Comments