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Steve9
New Contributor
1 month agoThank you for the link. Below image is what I see regarding hot plug. It states that the device supports addition/removal from system during run-time.
I am not sure if this means Hot Plug is supported functionally but assumes the hardware design prevents I/O from being toggled while device is now powered by for example gating the I/O by having an enable for the REF_CLK buffer that is tied to the Agilex power supplies "Power Sequence Done" signal or similar.
Can you please confirm Agilex7 F tile transceivers will not be damaged when Agilex 7 F tile hot plugged into system with like PCIe REF_CLK and PCIE data lines such that they are driven before the Agilex7 F tile is powered.