Forum Discussion
New ContributorLVDS Compatibility with GTS Refclk (CML / HCSL)
We are evaluating a use case where an LVDS clock source drives a GTS transceiver reference clock input, which is typically configured for CML or HCSL standards.
Is this usage supported, particularly when using AC coupling between devices, as seen on the Agilex 5 Premium Development Kit?
What are the required pin configurations and electrical considerations (e.g., termination, biasing) to ensure proper operation?
Does this approach present any known limitations or risks?
For reference:
- IO Standard for GTS Transceiver REFCLK (forum contribution)
- Agilex™ 5 FPGA E-Series 065B Premium FPGA Development Kit DK-A5E065BB32AES1 Board Schematic (88E2110_REFCLK is an example)
6 Replies
Ash_R_AlteraRegular Contributor
Hi,
In most high speed interface cases, the FPGA refclk pin is configured with CML IO standard to interface with the LVDS driver. HCSL is typically used in PCIe interfaces.
You can very well take the devkit as a reference to interface LVDS clock driver to GTS transceiver. It uses 0.1uF of AC coupling to adjust the common-mode voltage conflict. The termination (parallel 100 ohm) closer to the receiver set the correct bias.
Hope this helps.
Regards
- Ash_R_Altera
Please let me know if the provided solution resolves your issue.
Regards,
Altera Support
sbjHi,
is there a way to find out what pin configurations and electrical considerations (e.g., termination, biasing) are required to ensure proper operation?
Just some general documentation to have a better overview of what is inside the fpga and what needs to be added externally, would be very helpful.
Thanks
- Ash_R_Altera
Hi,
Please refer to the diagram in the following link showing the receiver buffer of Agilex 5 GTS. It shows Con-chip which is inside the FPGA and also Con-board, which user is supposed to put on the board.
As mentioned earlier, you may use the development kit as a reference. We recommend you to do a board level simulation to make sure that the signal integrity on the board design is good.
Regards,
Altera Support
- Ash_R_Altera
Kindly confirm whether the suggested steps have addressed your concern.
Regards
- sbj
All good. Thank you
