LVDS Compatibility with GTS Refclk (CML / HCSL)

We are evaluating a use case where an LVDS clock source drives a GTS transceiver reference clock input, which is typically configured for CML or HCSL standards.

Is this usage supported, particularly when using AC coupling between devices, as seen on the Agilex 5 Premium Development Kit?

What are the required pin configurations and electrical considerations (e.g., termination, biasing) to ensure proper operation?

Does this approach present any known limitations or risks?

For reference:

• IO Standard for GTS Transceiver REFCLK (forum contribution)
• Agilex™ 5 FPGA E-Series 065B Premium FPGA Development Kit DK-A5E065BB32AES1 Board Schematic (88E2110_REFCLK is an example)