GTS Transceiver PLL Usage

From the GTS Transceiver PHY User Guide:

“The GTS System PLL Clocks IP cannot be compiled or simulated as a standalone IP. It must always connect to the GTS PMA/FEC Direct PHY IP.”

• Does this restriction also apply when the parameter “Use case of System PLL” is set to “FABRIC_USE_CASE”?
• In this mode:
  • Is it mandatory to use output clock C1 to drive the FPGA fabric?
  • Are there other usable outputs?
• How can we determine the set of available output frequencies for C1?
  • What is the relationship between the output frequency and the selected reference clock (refclk)?