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mohandas3rditech's avatar
mohandas3rditech
Icon for New Contributor rankNew Contributor
7 days ago

MAX 10 FPGA POR trip Levsl and tRAMP

I am intending to use a 36 pin count dual power supply MAX 10 part for a lower power application. From Fig 3 of UG-M10PWR (pasted below), nStatus is asserted when POR trip level is met within tRAMP. The battery for my application may have a longer ramp up time than tRAMP (10 msec for my part). What is the consequence of this. Will device not come out of reset if tRAMP condition is not met? Are there any workarounds for this?

 

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1 Reply

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 hours ago

    Yes, if your battery ramp exceeds the specs of the MAX10 tRAMP, then the device may remain held in POR and fail to configure. This is mentioned in the same document you refer:

     

    Unfortunately, you need to ensure that the power supply ramp time meets the specification to allow the nSTATUS to be asserted.