Updated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!Is VCCPD = 3.3V and VCCIO = 2.5V allowed on an Arria V?
Hi, I am currently using an Arria V 5AGXMA1D4F27 device. I would like to use 3.3V on VCCPD and 2.5V on VCCIO for the IO bank. The intent is to have JTAG programming done at 3.3V(the processor doing the programming has 3.3V GPIOs). All pins on the bank will be using 2.5V for normal operation in addition to having true LVDS pins on the same bank after configuration. I could not find any documentation for this. It would be of great help to have a confirmation on if this is valid? Thank you for your time.
Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.
Cyclone IV drop in replacement confirmations
Dear Altera, If the BANK VCCIO is 1.8V and the same package but with different LE # FPGA is drop in replace. Where the original pin is a VCCA while different LE size same pin is a IO. With 1.8V on VCCIO and input fixed to VCCA aka 2.5V do this introduce any issue? As we can see the datasheet mentioned the DC input accept 3.6 or below. -> Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2) So the C4 device have a protection forward diode to clamp the voltage when IO is set to input? As long as that pin is fixed to input state do this condition function properly? Thanks, Brian
Fan for AGRW027 (Agilex 9)
Hello, When I power on the AGRW027 board, the board fans run at a particular speed. While I am downloading my bitfile (via JTAG) and my design is running on the board the fans go to a very minimum idle speed. How, do I keep the board fans running at an elevated speed. Regards, Neal
Arria 10SX current drawn during non-volatile key programming
Hi, we are using in our design an Arria10 SX (precisely the 10AS027E4F29E3SG) device. The design had been successfully manufactured for approx. 100 units. For one customer we decided to use design security and started to program a non-volatile key into the FPGA and use encrypted bitstreams later on. It turned out that appox every tenth unit failed now because the power manager found either an excessive current on the global supply or the VCCPT (1.8V) was degraded while programming the non-volatile key. Note, the supply driving the VCCPT had been designed to provide +70% current as calculated by the Quartus power analyzer (by the way it did not help that this support had been removed for Arria 10 from Quartus Pro, I did not check which versions actually support it, 18.1 works, 23.2 fails). Thus there is a reserve of approx 550mA at the supply. It obviously comes to its limits during the non-volatie key programming. I searched (again) for a specification in the Altera Arria 10 documentation (mainly datasheet, handbook and AN556) which current is drawn on which supply while programming the non-volatile key. I did not find any information on that. Can you please point me to the documentation where I can find this specification or can you provide me the numbers? Even an estimate will help. Thank you! Gerhard
URGENT SUPPORT FOR FMD DATA COLLECTION
Hi Team, I am Siddesh Chavan from the NetApp Component Engineering Team. As part of our component compliance review and documentation update process, we are reviewing the Lotes Co. Ltd part. We kindly request your support in providing the information requested for the components listed in the attached file. Please acknowledge receipt of this email and confirm whether you can provide the requested details. Your support will help us keep our records accurate and up to date. Thank you for your support and cooperation. We look forward to your response. Regards, Siddesh Chavan
Altera PDN Tool Decoupling Capacitors Results
To whom it may concern, Would you please provide the schematics of the following refence design: https://www.intel.com/content/www/us/en/content-details/632722/intel-enpirion-power-solutions-reference-design-for-arria-10.html The reason for this is that when the VRM models of the Enpirion regulators that are used in the abovementioned reference design are entered into the Altera PDN tool, the PDN tool returns zero decoupling capacitors for the Arria 10 core voltage and a small number of capacitors for the other voltage rails. We are using high performance voltage regulators in our Arria 10 SX design (with the VRM models entered into the Altera PDN tool), in which the Altera PDN tool produces decoupling capacitors results that are similar to the ones obtained when the VRM models of the Enpirion regulators are used in the tool. Therefore, would you please provide us with the schematics of the abovementioned reference design so that we get a reassurance. Is it common that the Arria 10 core voltage only requires a small number of bulk decoupling capacitors (approaching zero) and no small value capacitors when the host PCB is optimized and high performance voltage regulators are employed due to Ftarget and Ztarget of the core voltage? Kindly, advise. Regards, F