Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster
Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode. My current doubt is regarding the pull-up voltage for JTAG and USB Blaster: Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..? As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct. For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect. Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6? Please respond at the earliest. If you need any clarification, feel free to ask. Thank you!97Views0likes7CommentsCYCLONE 10LP Decouple capacitors
Hi, Im designing board with 10CL120YF780 and try to understand which decoupling capacitors i should use. All the banks works on 3.3V (about that, also the configure bank can use this voltage, JTAG&FLASH, right?) F = 200MHz VCCIO (1-8): 3.3V, 0.1A max, 3.75V max OV VCCINT: 1.2V, 2A max, 1.8V max OV VCCD_PLL: 1.2V, 0.2A max, 1.8V max OV VCCA: 2.5V, 0.1A max, 3.75V max OV Please your help with that (the PDN xls doesn't work for some reason on my computer) Thanks58Views0likes4CommentsThe Verilog code was not actually programmed into the FPGA.
I have a question. I am using a 10M02SCM153C8G FPGA. I wrote a simple program, successfully programmed it onto the development board, and confirmed it produced the intended simple functionality. However, I've noticed that whenever I power cycle the evaluation board (by unplugging and replugging the USB cable), the board reverts to running the original sample code that was pre-loaded. This leads me to believe that although I performed the programming operation, the code was not actually programmed into the FPGA's non-volatile memory. Is there a specific option in the programming interface that I must select to ensure the code is permanently written to the FPGA's internal Configuration Flash Memory (CFM) block? As I recall, the MAX 10 series does not require an external SPI EEPROM for configuration, which I believe is correct. Does this also mean that if I do not select the correct programming option, the code is only loaded into the FPGA's volatile SRAM, and is therefore lost upon power-off?54Views0likes5CommentsDelay in SPI-to-Avalon-MM IP Response After MAX10 Reset
Hello everyone, I’m using the SPI-to-Avalon-MM IP to enable communication between an external microcontroller (MSP430) and a MAX10 FPGA (MAX10M50DAF256CG). In my setup, the microcontroller acts as the SPI master, and the FPGA is the slave. The microcontroller also controls a GPIO line connected to a load switch, allowing it to power the MAX10 on or off. The FPGA receives a 26 MHz external oscillator input, which feeds into a PLL. The PLL’s lock signal is used to generate a system reset. Here’s the behavior I’m observing: even after the PLL lock signal asserts and the system leaves reset (measured by routing the lock signal to an external FPGA pin and timing from the moment CONF_DONE goes high), it still takes around 9 ms before the FPGA and the SPI-to-Avalon-MM IP start responding to SPI messages from the microcontroller. My questions are: What could be causing this post-reset delay? Is there a defined startup time for the FPGA and IP to begin responding? I haven’t found documentation on this—are there any relevant resources? Thanks in advance for your help.Solved520Views0likes1CommentMAX 10 Instant-On
Hello, I understand the instant-on timing specs to be relaxed per this adjacent post - https://community.intel.com/t5/Programmable-Devices/MAX10-Instant-On/m-p/202216 However, for the sake of deeper understanding, can you please point Me to document #683794 version 2017.12.15 or advise further? I'd like to better understand what was once considered. Thank you,472Views0likes1CommentCyclone 10 GX continiously increasing power consumption
Hello, We developed two custom evaluation boards (different layouts) using the Cyclone 10CX150YU484E5G FPGA . Our problem is that we face the same increasing power consumption issue in both development boards. Before and after the FPGA placement we measured all the point of loads on the PCB and there was no short circuit. The FPGA is biased correctly in every pin. We also followed the guidelines for the power-up sequence. After placing the FPGA we stated the following issues: 1.The un-programmed FPGA increased gradually the current consumption of the boards and it was also heated a lot. 2. Before the FPGA programming the GPIOs of all the banks outcome "high" values. 3.After the successful FPGA programming through JTAG and AS the rate of the current consumption dramatically increased. Do you have any ideas regarding the cause of this behavioral in any of the above mentioned issues ? Regards,912Views0likes5CommentsExtra Power adaptor for Agilex™ 7 FPGA M-Series HBM2e Development Kit
Hi, To start using the Ethernet (except loop-back), the documentation writes: "All the QSFPDD and QSFPDD800 ports can support up to class 8, meaning each port consumes 18 W. Two power supplies are needed to provide sufficient power for peak performance." (section 3.2). I have looked to buy an identical one that is supplied with the kit, but they seem hard to find, and alternative power adapters that are 12V/250W (like the one supplied with the kit) with a PCIe (Molex Mini-Fit Jr.) connector is hard to find. Could you kindly advise on where to find such power adapters? Thanks in advance.672Views0likes3Comments