Cyclone V 2.5V LVPECL vs LVDS inputs
When feeding an AC coupled LVPECL differential signal into a Cyclone V FPGA, the Cyclone V datasheet appears to indicate that DC bias and OCT 100 ohm differential termination is not available when Assignment editor specifies differential I/O as LVPECL. Furthermore, LVPECL inputs are limited to CLK input pins. Questions: 1. Are my comments above correct? 2. Per Cyclone V datasheet LVDS I/Os appear to be able to receive an AC coupled LVPECL signal which would enable internal chip provided DC biasing and OCT 100 ohms by simple Assigning LVPECL input to LVDS in Assignment editor. Is this true? Are there any negatives? Thank you in advance, Tony
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster
Hi Team, I am working with a Cyclone IV E FPGA(EP4CE30), where all my banks (Bank 1–8) have VCCIO = 3.3V. The FPGA core voltage is 1.2V, and the PLL supply is 2.5V. I am configuring the FPGA in Passive Serial (PS) mode. My current doubt is regarding the pull-up voltage for JTAG and USB Blaster: Should the pull-up resistors be tied to 2.5V or 3.3V? What should be the pullup voltage for MSEL Pin..? As per the Hardware Design Guidelines, my understanding is that the pull-up supply should match the VCCIO of the respective bank. Please confirm if this is correct. For your review, I have attached a snippet of the Configuration Pin Schematic. Kindly check and let me know if anything looks incorrect. Additionally, for the 10-pin male header, what should be the voltage level for Pin 4 and Pin 6? Please respond at the earliest. If you need any clarification, feel free to ask. Thank you!
Does direct connection of two AXI4 Masters to DDR Slave support auto-arbitration on Agilex 5?
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？Signal Tap false trigger
I'm using Quartus Signal Tap to capture waveforms and encountering a false triggering issue (triggering when the trigger condition is not met, for example, trying to capture the moment when a signal that is constantly low becomes high, but it captures incorrectly). When this false trigger occurs, only half of the waveform is displayed (only the waveform after the trigger position). Has anyone experienced a similar problem? How can this be resolved? (Agilex 7 using HPS)
Cyclone 10 LP's Extended Industrial parts
[Question] Customer have questions about Cyclone 10 LP's Extended Industrial (Tj = -40degC to 125degC) in the Product Catalog at the following URL. https://www.intel.com/content/www/us/en/content-details/730595/altera-product-catalog.html What is part number of Extended Industrial of "10 CL010YM164I7 G" as part number of Normal Industrial? What should the customer do if they want to check the power consumption by EPE(Early Power Estimator)? How can the customer design with Extended Industrial part if they want to compile with Quartus? Best Regards
MAX10 DDR3 Timing
Hi, I need a definitive statement regarding the timing. The two attached screenshots were created with Quartus 23.1 but can also be found in 25.1. Although adjusting the temperature range reduced the number of failing paths (see screenshot 800MHz_300MHz_DDR3_1, which ran at -40°C to 100°C), there remain parts that do not meet the timing. According to the datasheet, this should work. The MAX10 being used is a 10M16DAF484I6G, which is the fastest speed grade. The memory is Micron MT41K256M16TW-107AAT. Br, KorbinianDebugging the FPGAs connected in passive serial mode
I have two cyclone 3 devices(EP3C16F484C8 & EP3C5F256C8) which is connected in passive serial mode. I wanted to debug the device and only JTAG connection is available to do so. I don't want to change anything in the code and i don't want to reprogram, I don't want to use signal tap either. How can i debug the devices while the device is running? My device frequency is 26 mHz, but most of my outputs changes 10 times in 15s but it is ruled by 26 MHz frequencyLVDS support on Agilex 7
HI, Im working on INTEL AGILEX 7 F-SERIES X2 F-TILE FPGA. Please clear my doubt In True differential signalling of LVDS , it is mentioned as differential signal with common mode voltage of 1.4 you can have only 100mV swing. So you are limiting it to only 1.5V including the swing. if i have a secondary device and it has common mode voltage of 1.375V and swing can be 200mV.So , my full swing voltage is going to be 1.575V. Will this signal , can be captured by FPGA GPIO pin or not? Whether it will damage ,my pins in FPGA?
