Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel Altera, I would like to confirm that the 6 channels GXB device: Q1) Do it possible to use all 6 TX / RX GXB Transceivers when Hard PCIe is used. Based on: CV-53004 There are no specific diagram to explains the single PCIe hard core device with only 6 channel case. Q2) Based on the document: CMU PLL will use CH5 and do this simply means there will be one extra for PCIe Hard-Core? Q3) If not understood falsely, Either PCIe X2 GEN1 + 4 custom GXB usage nor PCIe X4 GEN1 + 2 custom GXB usage is possible? And most protocol uses 1,2,4 and the only possible case is PCIe X4 GEN1 + 1 custom GXB? A little more info from CV-53002 So in order for PCIe Hard Core to run x2 or x4 CH4 must be used. As a result for custom TRX there is no way to use CH1 when PCIe is > x1? Thanks, Brian
writing a word to cfm1 using on chip flash ip on max10
hii i have the neek board development kit , and i am writing my own logic to perform a writing of an image to cfm1 flash sector for remote update i am transferring the image through uart from rpd file just like in nios rsu example lab . i configured the on chip flash ip in this parameters data interface :parallel read burst mode :incrementing read burst count:8 configuration mode :dual compressed images i set the burstcount to 1 I managed to erase the CFM1 sector, and I read the status register to confirm that the erase of sectors 3 and 4 was successful. Sector 3 + 4 corresponds to CFM1. Before performing the write operation, I verify that the on-chip flash is in the idle state by reading the CSR status register. I place the word on the data_writedata signal of the Avalon bus with the correct address, assert the data_write signal, and then wait until waitrequest goes low before proceeding to the next word. I confirm that the write was successful by reading the ‘write successful’ bit in the CSR status register. but sometimes in the middle of the file transfer , i get a write failure and i am not sure why , my clock on board is 50 mhz and i am using pll to generate 75mhz. so i i am feeding the 75mhz clock to the on chip flash ip and my own writing fsm logic Using SignalTap, I can see that the word before the one where the write failed was written successfully. I send each word over the UART interface with a delay of 2.5 ms, which I believe is sufficient for the write to complete. I also check the waitrequest signal before proceeding to the next word and verify that the on-chip flash is in the idle state.” I would be thankful to know why I am getting a write failure and what I should check to resolve this issue? thanks
Agilex 7 HBM2E burst length
I noticed that I can use a burst length of 1 (arlen/awlen = 0). But the datasheet says "In BL8 mode, the HBMC supports only a burst length of 2 for write and read transactions. If you issue a burst length of 1 in BL8 mode, you will see bresp="10"(SLVERR).". Is the datasheet outdated (for version 25.1.1, didn't find one for 25.3.1 which I'm currently using), or is this undocumented and I shouldn't do this? Would make programming easier, if also burst length 1 is supported.Agilex5 / IBIS HSIO - LPDDR4
Hi, number of IBIS models for banks HSIO listed in ag-5-device-list-of-ibis-models.xlsx, is very important (several thousands). We are interfacing LPDDR4 on our HSIO banks at standard LVSTL11 single and diff. When generating an EMIF IP for that need, without touching defaults parameters (hereafter) , which are IBIS models to use among that list ? We are supposing « lvstl11_io_s3r40c_doff » and « dlvstl11_io_s3r40c_doff ».
Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue
Hi, I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me. Thank you
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
Stratix 10 fPLL pre-calibration
We need to switch (reconfigure) the Stratix 10 fPLL clock rate without waiting for its automatic calibration. For the Arria 10 we disable the automatic calibration and, after power-up, we command a "manual" pre-calibration, read the calibration results from fPLL registers and store the calibration results in our temporary registers. We do that for a number of clock rates and create a table of calibration results. Then, when clock rate needs to be changed, we just rewrite the calibration results from our temporary registers back to the fPLL registers, choosing the correct clock rate. This is much faster and works very well. For the Stratix 10 we would like to know what are the addresses and the bit masks of the calibration result registers we need to store and to rewrite.R-Tile Avalon Streaming PIPE Direct x16: Locks COM(K28.5) Symbols correctly but some lanes do not.
Hello, I am implementing a custom soft PCIe/CXL link layer and LTSSM using R-Tile Avalon Streaming IP in PIPE Direct mode, configured as x16. At the moment, link training does not reliably move forward because some lanes receive valid COM/K-code alignment, but the following ordered-set symbols are corrupted. Environment Device / board: AGIB027R29A IP: R-Tile Avalon Streaming FPGA IP for PCI Express Mode: PIPE Direct Link width: x16 Current focus: Gen1 training / Polling / Configuration Custom implementation: custom LTSSM custom symbol lock using COM (K28.5) custom TS1/TS2 decode logic Symptom In Polling.Active and Polling.Configuration , I can see that some lanes captures/decodes TS1/TS2 correctly, but some lanes do not. For example, in the attached SignalTap screenshot: Lane 9 appears to decode the TS2 sequence correctly. Lane 8 shows COM (K28.5) and PAD (K23.7) correctly, but the symbols after that are unstable / corrupted. From the screenshot: Lane 9 example: K28.5, K23.7, K23.7, D24.0, D30.0 D00.0, repeated Lane 8 example: K28.5, K23.7 are visible, but the following TS2 fields fluctuate and do not remain valid/stable. So it looks like: COM-based symbol lock is working at least partially but after COM/PAD, the ordered-set contents on some lanes(random) are corrupted before my soft IP can decode them correctly To verify whether this was caused by my own logic, I captured the affected lanes directly in SignalTap using the first raw 10-bit RX data from the PIPE Direct IP (`ln*_pipe_direct_pipe_rxdata_o`), before any symbol lock/decoding stage in my soft IP. I searched for the COM symbol directly in this raw 10-bit stream and confirmed that the corruption is already present at the PIPE Direct IP output. So this does not appear to be caused by my combinational decode logic; the raw RX data delivered by the IP is already corrupted on those lanes. What I already checked I already checked the following items carefully: Gen1 rxdata interpretation I only decode valid 10-bit portions for Gen1 I do not interpret the don't-care bits in rxdata[31:10] and rxdata[63:42] rxdatavalid qualification TS decode / symbol shift only happens when rxdatavalid0/1 are valid Sampling clock SignalTap capture is done in the corresponding lane RX clock domain not with a shared TX/fabric clock Reset sequence pld_pcs_rst_n_i release is gated after per-lane tx_transfer_en_o I also reviewed cdrlock2data, reset_status_n, phystatus, powerdown sequencing Deskew-related status active channels are detected Current question At this point, I suspect one of the following: lane-specific analog/RX quality issue inside or before PIPE Direct output lane-specific reset/power-up timing issue internal alignment / deskew behavior that I am misunderstanding some required PIPE Direct control/sideband setting that I am missing What I would like to ask In PIPE Direct x16 Gen1, if one lane shows valid K28.5 / K23.7 but the following TS2 symbols are corrupted, what should I check first on the R-Tile side? Are there any lane-specific PMA / RX / PIPE Direct controls that should be reviewed for this symptom? Is there any recommended way to determine whether this is: a true lane analog/RX problem, a deskew/alignment issue, or a reset/bring-up sequence issue? Are there any known recommendations for validating lane integrity directly at the PIPE Direct output during Polling.Configuration?Timing Slacks inside Altera IP
Hi, I am compiling my design for the device 10AX115N2F40I2SG using: Quartus Version: 22.1std.2 (Build 922, 07/20/2023, Standard Edition) I am encountering timing violations (negative slack) on the clock a10_internal_oscillator_clock0 across all synthesis seeds. Due to these violations, I am unable to close timing on my design. From my analysis, the failing paths appear to be internal to the Intel (Altera) IP, for example: From: ddr3_phy_wrapper48:ALTERA_DDR.ddr3_phy_wrapper_u|se_phy_master:u_qm2_phy|se_phy_master_altera_emif_221_zihdyxy:emif_0|se_phy_master_altera_emif_arch_nf_221_lnlpemi:arch|se_phy_master_altera_emif_arch_nf_221_lnlpemi_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|iopll_bootstrap:gen_pll_dprio.inst_iopll_bootstrap|gen_pll_dprio.r_dprio_writedata_in_use~RTM To: |ddr3_phy_wrapper48:ALTERA_DDR.ddr3_phy_wrapper_u|se_phy_master:u_qm2_phy|se_phy_master_altera_emif_221_zihdyxy:emif_0|se_phy_master_altera_emif_arch_nf_221_lnlpemi:arch|se_phy_master_altera_emif_arch_nf_221_lnlpemi_top:arch_inst|altera_emif_arch_nf_pll:pll_inst|pll_inst~dprio_reg My understanding is that this clock is only active during PLL calibration at device power-up and is not used during normal functional operation. Given this, I would like to confirm whether it is safe and appropriate to constrain these paths as false paths. For example: "set_false_path -from [get_clocks {a10_internal_oscillator_clock0}]" Could you please advise if this approach is valid, or if there is a recommended way to properly constrain these paths? I attached an image of the slacks.MAX10 RSU upgrade succeeds, but device boots Factory image instead of Application
Hello, I’m using Intel MAX10 Remote System Upgrade (RSU) with: CFM0 = Factory CFM1 = Application The firmware‑triggered RSU upgrade completes successfully, but after reconfiguration the device boots back into the Factory image instead of the Application image. Below is the design setup: RSU IP instantiated and connected over SPI Avalon‑MM master interface of RSU IP is exported to user logic onchip_flash data interface is also exported and visible in the top level Firmware performs erase/write/verify through the exported Avalon‑MM interface Autoboot decision is based on a bit stored in UFM, read at startup No external power cycle occurs during RSU (warm reconfiguration). Below are the observations: RSU programming via firmware completes without errors MAX10 reconfigures after RSU Cold boot works correctly Programming the App image via JTAG works Issue occurs only after warm RSU (no power cycle) Autoboot selection is controlled via a bit stored in UFM. For this I have exported the AV-MM I have the below questions: Is it expected that RSU does not automatically re‑enter autoboot logic? After warm RSU, must user RTL explicitly regenerate a boot / autoboot event? Are there recommended MAX10 reference patterns for autoboot handling after RSU? Thanks for any guidance or references.
