New Contributor[Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout
Device: Agilex 5
Issue Description: The Timing Analysis report indicates that a specific PLL output clock has a fanout of 21343(see screenshot below). Does this high fanout on non-global routing imply that the clock failed to be promoted to the Global Clock Network?
Suspecting this was the issue, I configured the "Global Signal" assignment to "On" in the Assignment Editor and recompiled the design. However, this setting appears to be ineffective，the fanout still 21343.
【set_instance_assignment -name GLOBAL_SIGNAL ON -to u0|clock_subsystem|iopll|iopll_1|tennm_ph2_iopll~O_OUT_CLK0】
Could you please advise if this needs to be addressed and how to successfully enforce the Global Clock assignment?
Thanks.
I think they're same signal and had been pushed to global clock network. If you turn off global signal, the signal is not showed in Fitter's 'Global & Other Fast Signals' summary right?
For clock, it's normal and healthy to still have high fanout even though had been pushed to global clock network (clock usually having high fanout). The global clock network will have low skew for those clock high fanout.
The only problem is the high fanout clock but using regional routing, that'll causes skew issue.
