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New Contributor[Agilex 5] Global Clock assignment ignored for PLL output clock with high fanout
I think they're same signal and had been pushed to global clock network. If you turn off global signal, the signal is not showed in Fitter's 'Global & Other Fast Signals' summary right?
For clock, it's normal and healthy to still have high fanout even though had been pushed to global clock network (clock usually having high fanout). The global clock network will have low skew for those clock high fanout.
The only problem is the high fanout clock but using regional routing, that'll causes skew issue.
New ContributorThe picture is from the Fitter's 'Global & Other Fast Signals' summary. I believe this entry corresponds to the manual constraint I applied in the Assignment Editor.
Could you please confirm if this is effectively the same signal as the one reported with a high fanout of 21,343 in the Timing Analyzer?
Please advise. Thanks
Super ContributorI think they're same signal and had been pushed to global clock network. If you turn off global signal, the signal is not showed in Fitter's 'Global & Other Fast Signals' summary right?
For clock, it's normal and healthy to still have high fanout even though had been pushed to global clock network (clock usually having high fanout). The global clock network will have low skew for those clock high fanout.
The only problem is the high fanout clock but using regional routing, that'll causes skew issue.
- wangduoyu
I got it，thank you
