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DE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? Thanks110Views0likes12CommentsFlash Loader IP not loaded on device 1?
Hello, I have a Cyclone IV based FPGA board (LimeSDR-PCIe v1.3) I am trying to flash FPGA FW but in Quartus I always get this error. "Flash loader IP not loaded on device 1" see log below. /altera_lite/15.1/quartus/bin$ quartus_pgm -m jtag -o "ipv;./LimeSDR-PCIE_lms7_trx_HW_1.3.jic" Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 15.1.2 Build 193 02/01/2016 SJ Lite Edition Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Apr 22 13:06:06 2020 Info: Command: quartus_pgm -m jtag -o ipv;./LimeSDR-PCIE_lms7_trx_HW_1.3.jic Info (213045): Using programming cable "USB-Blaster [1-2]" Info (213011): Using programming file ./LimeSDR-PCIE_lms7_trx_HW_1.3.jic with checksum 0x7273C3BF for device EP4CGX30CF23@1 Info (209060): Started Programmer operation at Wed Apr 22 13:06:07 2020 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x028230DD Info (209007): Configuration succeeded -- 1 device(s) configured Error (209062): Flash Loader IP not loaded on device 1 Error (209012): Operation failed Info (209061): Ended Programmer operation at Wed Apr 22 13:06:11 2020 Error: Quartus Prime Programmer was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 411 megabytes Error: Processing ended: Wed Apr 22 13:06:11 2020 Error: Elapsed time: 00:00:05 Error: Total CPU time (on all processors): 00:00:01 Can anyone guide me what the issue could be, Is there some file missing? The repo is available here: https://github.com/myriadrf/LimeSDR-PCIe_GW I am using Quartus Lite 15.1.2 Build 193. Thanks.7.9KViews0likes8CommentsStratix IV GX Development kit 530 edition software
Dear Team, I'm trying to donwload the Stratix IV GX Development Kit 530 Edition software installer, but the links don't work anymore. https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-siv-gx.html Is possible that you reupload it or send me a link for download it? Thank you!!24Views0likes0CommentsEPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!39Views0likes3CommentsAbout old Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
I can see that the old version of Quartus has come back, so I will give it a chance. Could Altera offical upload the "SIIGX_SI_Kit-v1.0.1.exe" file again for "Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board"? Any help would be appreciated.14Views0likes1CommentProcess for RMA - Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Hello there, I have an Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (https://www.altera.com/products/devkit/a1jui0000049utomam/agilex-7-fpga-i-series-transceiver-development-kit-6x-f-tile) that has recently stopped functioning correctly. In particular, the JTAG chain does recognize the existence of the Agilex FPGA. Quartus's JTAG debugger throws an error: Error: TDI connection to the first detected device 10M16S(A|C|L) might be shorted to GND Error: The TCK and TMS connections to the device before the first detected device 10M16S(A|C|L) might have a problem Info: Detected 1 device(s) Info: Device 1: 10M16S(A|C|L) When trying different settings on the JTAG chain selection mux, it is clear that the System MAX10 is detected and functioning correctly, but the Agilex FPGA cannot be detected. We have tried to reprogram the MAX10 with the factory default image, but there has been no change. We suspect a hardware issue with the JTAG chain. At this point, the Agilex FPGA is not accesible, rendering the board unusable for our purpose. Could ALTERA please support us on this? Is it possible to start the process for an RMA? Are there any options that we can consider? We greatly appreciate your assistance in this time of need Thank you20Views0likes1CommentJTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.29Views0likes3CommentsEMIF HPS errors after upgrading to Quartus 25.3
So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1. Firstly, when upgrading to Quartus 25.3, the auto-update does not work with errors to the Agilex-5 HPS IP and EMIF HPS IP. I'm forced to upgrade manually which also results in errors but fixed with this workaround: https://www.intel.com/content/www/us/en/support/programmable/articles/000102053.html In the end I can Generate HDL sources from Platform Designer but compilation stops with errors in the Fitter stage: I've noticed that the new EMIF HPS IP version has a difference in the signal mem_0_bg that only has 1 bit in the latest version but was 2-bit wide in the previous versions. I don't know if the problem comes from this: Another interesting thing that I found is that in the latest GSRD project (QPDS25.3_REL_GSRD_PR) the EMIF HPS IP used is not the latest version (4.1.0) but a previous one (4.0.0). So I'm guessing someone from Altera already discovered some sort of problem here: Looking for advice on how to proceed.Solved36Views0likes3Comments