Recent Discussions
AXC3000 Agilex 3 board
Hi, for a new design I'm starting to use an evaluation board from Arrow Electronics, (but designed by trenz electronics) with Agilex 3 https://github.com/ArrowElectronics/Agilex-3/wiki/Agilex-3-AXC3000-Development-Platform This board has an Hyperam W957D8NBRA4I installed but the Nios V example design uses only internal RAM. Anyone knows if the IP to use this ram is free into quartus or is necessary to acquire a license? Thanks
DK-DEV-AGI027RES Install Package
I'd like to download an old outdated install package. It is for DK-DEV-AGI027RES. The link was removed a while back. Can someone at Altera please find the install package for me? A .qsf file with all the pinouts (e.g. golden_top.qsf in the install package) defined would work too.
Agilex 5 reconfigurable PLL - emif
Trying to reconfig a PLL with the EMIF Calibration IP debug via system console Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs enabled dynamic config within IOPLL and included EMIT Calib. writing to divide setting addresses -> changes are immediate multiple pure phase shifts did not work (work randomly) is there a bit to start the shift with one design setting N - M - C worked but no multiple shifts with an other design problems writing to 0x80 to reset pll after setting NMC, no replay for new nmc setting 6.4.1 enable | 6.4.2 clear calib | 6.4.3 reconfig | 6.4.4 recal for just phase shifting 6.4.1 read modify write 6.4.3 without 0x80 2.2.12 perform positive or negative phase shift - is there a bit for that? Where did I go wrong?
Regarding data for the Altera Arria V GX FPGA development kit
I am looking for information on an Altera Arria V evaluation board that is equipped with the SFP module. I think that Arria V GX FPGA Development Kit is the relevant product. However, when I check the links below, I see “Error 404: Page Not Found.” Are the following links incorrect? Arria V GX FPGA Development Board Reference Manual (English, PDF) http://www.altera.com/literature/manual/rm_avgx_fpga_dev_board.pdf Arria V GX FPGA Development Kit User Guide (English, PDF) http://www.altera.com/literature/ug/ug_avgx_fpga_dev_kit.pdf Kit installer ftp://ftp.altera.com/outgoing/devkit/12.0/arriaVGX_5agxfb3hf40es_fpga_v12.0.0.exe Please provide the correct links. Best regards, Hachiware.
Agilex7 m-series for llama
I am undertaking a project to deploy llama using the agilex7 m-series, and during the process, I utilized the FPGA AI Suite. However, dla_compiler does not support the sinking of graphs to FPGA. Could it be that the gather operator is not supported, or is it because the tensors have dynamic dimensions? This prevented me from generating the .bin file suitable for the FPGA. In addition, the FPGA AI Suite does not provide the ARCH file for HBM, and the list of selectable devices for the plugin does not include the M-series. Could you provide some BSP support instead?
LLM Implementation on Agilex 5 E-Series 065B Modular Dev Kit
I am currently working on deploying Large Language Model (LLM) inference using FPGA AI Suite on the Agilex 5 E-Series 065B Modular Development Kit. I have two clear and specific questions: Is the Agilex 5 E-Series 065B officially supported for LLM / Transformer inference with FPGA AI Suite? Is the following workflow officially supported for LLM inference on this board? Step 1: Export a pre-trained LLM from Hugging Face to OpenVINO IR format using optimum-intel Step 2: Generate the target FPGA architecture file using architecture_optimizer for Agilex 5. Step 3: Compile the OpenVINO IR model for the FPGA using: • dla_compiler → for Sequential flow, or • Spatial Compiler → for Spatial flow. Step 4: Integrate the generated FPGA AI Suite IP into a Quartus Prime project, generate the bitstream, and program it onto the Agilex 5 E-Series 065B board. Step 5: Run inference using the FPGA AI Suite runtime (host application). I understand this may not be a push-button process and could require significant modifications to the generated RTL — but is this workflow still considered a viable starting point for implementing LLM / Transformer inference on the Agilex 5 E-Series 065B? Thank you.Fitter error in A5ED043AB23AI2V Example design
Hi, I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V. During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually. Could you please help me understand how to resolve this issue?Example design for [MAX 10 User Flash Memory (UFM) Data Incrementing Burst Read Mode].
Hello. Thank you for your help. I would like a example design for [MAX 10 User Flash Memory (UFM) Data Incrementing Burst Read Mode]. https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/max10ufm-incrementing-burst-read-ug.pdf However, I cannot find the design website link referenced in this document. Please provide the design described in this document. Additionally, the following link does not contain MAX 10 Example Designs. Please provide a website link that contains all MAX 10 Example Designs. https://altera-fpga.github.io/rel-26.1/ed-demo-list/ed-list/ Best regards, Hachiware