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yolov3_tiny_tf run_inference_stream problem
i have completed successfully Arria 10 SoC demo project resnet-50-tf on Arria 10 SoC devkit. (my tool version intel fpga ai suite 2025.1 and open vino 2024.6). i have used the precompile arria10 wic image. Arria 10 SoC devkit: https://www.altera.com/products/devkit/a1jui0000049utgmam/arria-10-sx-soc-development-kit SoC Demo project: https://www.intel.com/content/www/us/en/docs/programmable/848957/2025-1/soc-design-example-prerequisites.html Then, i have compiled yolo_v3_tiny_tf model with no folding and device fpga, cpu to obtain .bin file. When i run the ./run_inference_stream.sh, it get this error: root@arria10:~/app# ./run_inference_stream.sh Runtime version check is enabled. [ INFO ] Architecture used to compile the imported model: A10_Performance Using licensed IP Read hash from bitstream ROM... Read build version string from bitstream ROM... Read arch name string from bitstream ROM... Runtime arch check is enabled. Check started... Runtime arch check passed. Runtime build version check is enabled. Check started... Runtime build version check passed. Exception from src/inference/src/cpp/core.cpp:184: Exception from src/inference/src/dev/plugin.cpp:73: Exception from src/inference/src/dev/plugin.cpp:73: Exception from src/plugins/intel_cpu/src/utils/serialize.cpp:145: [CPU] Could not deserialize by device xml header. How can i solve this problem? Thank you. Note: root@arria10:~/app# ls build_os.txt libopenvino_auto_batch_plugin.so build_version.txt libopenvino_auto_plugin.so categories.txt libopenvino_c.so dla_benchmark libopenvino_c.so.2024.6.0 hetero_plugin libopenvino_c.so.2460 image_streaming_app libopenvino_ir_frontend.so libcoreDLAHeteroPlugin.so libopenvino_ir_frontend.so.2024.6.0 libcoreDlaRuntimePlugin.so libopenvino_ir_frontend.so.2460 libformat_reader.so libopenvino_jax_frontend.so libhps_platform_mmd.so libopenvino_jax_frontend.so.2024.6.0 libopencv_core.so.4.8.0 libopenvino_jax_frontend.so.2460 libopencv_core.so.408 libopenvino_pytorch_frontend.so libopencv_highgui.so.4.8.0 libopenvino_pytorch_frontend.so.2024.6.0 libopencv_highgui.so.408 libopenvino_pytorch_frontend.so.2460 libopencv_imgcodecs.so.4.8.0 libopenvino_template_extension.so libopencv_imgcodecs.so.408 libopenvino_tensorflow_lite_frontend.so libopencv_imgproc.so.4.8.0 libopenvino_tensorflow_lite_frontend.so.2024.6.0 libopencv_imgproc.so.408 libopenvino_tensorflow_lite_frontend.so.2460 libopencv_videoio.so.4.8.0 plugins.xml libopencv_videoio.so.408 results.txt libopenvino.so run_image_stream.sh libopenvino.so.2024.6.0 run_inference_stream.sh libopenvino.so.2460 streaming_inference_app libopenvino_arm_cpu_plugin.so
Looking for guidance on CXL IP access (university research, Agilex 7 I-series)
Our lab is currently conducting research on CXL-based systems, and we would like to use Altera’s CXL IP in our work. We already have an Agilex 7 I-series Development Kit, and we intend to integrate the CXL IP for non-commercial, academic research purposes only. However, when we contacted distributors such as Mouser and Digi-Key, we were informed that CXL IP is not available for sale in Korea now. Could you please let us know: 1. Whether CXL IP is available under a university license or academic program, 2. What the procedure is for a university in Korea to obtain or purchase the CXL IP (including any required forms, NDAs, or eligibility criteria), If there is a specific sales representative or regional contact we should speak with, we would appreciate it if you could connect us or share their contact information. Thank you very much for your time and support. I look forward to your guidance.
DE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? Thanks
JTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.
DK-DEV-AGI027RES Install Package
I'd like to download an old outdated install package. It is for DK-DEV-AGI027RES. The link was removed a while back. Can someone at Altera please find the install package for me? A .qsf file with all the pinouts (e.g. golden_top.qsf in the install package) defined would work too.
DE10-nano HPS boot from EPCS
Hello, I am currently trying to setup LoanIO on a DE10-nano so i can access the PHYs RGMII0 signals from the FPGA. According to the Cyclone V Manual, the HPS registers have to be set up in the preloader for this. So i follow this guide to build the u-boot-spl: https://www.rocketboards.org/foswiki/Documentation/UpdatePreloaderUBootOnDE10NanoOnWindows10OS Then converted it to a .hex file to initialize the on-chip Memory following to this guide: https://www.rocketboards.org/foswiki/Documentation/BootFromFPGA150 Then recompile the design and finally generate the .jic file to configure everything from EPCS64. Now the FPGA part of my design is running but the preloader does not seem to be executed. I am using Quartus Prime 24.1std and u-boot branch socfpga_v2025_07. I also tried setting SPL_TEXT_BASE to 0xC0000000 and CONFIG_SPI_BOOT inside the menuconfig. Am i missing any relevant flags or is the problem elsewhere? Best regards.
FFT Intel FPGA IP
When I use FFT Intel FPGA IP (version 19.1), the simulation results of fft is correct (compared with python calculate results). Then I assert inverse signal to calculate ifft, the results is incorrect. Note that the configuration of the IP is as follows. Can you tell me why the error happens, and how to solve this problem, thanks.