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VIASAT- Request for MDDS and REACH COC-176523
Dear Team, Greetings!!! Can you please provide Latest REACH COC and MDDS documents for below listed products. Manufacturer Part Number Part Description 1SG165HN2F43I2VG IC,FPGA,STRATIX 10,1624 K LES,48 XCVR,H-TILE,I TEMP,-2 SPEED, VID,1760 PINS,43 MM BGA,ROHS 1SG280HU1F50I1VGBK IC,FPGA,STRATIX 10 GX,2,800K LE,96 XCVR,H-TILE,SMARTVID STD PWR,BLACK KEY PROVISIONING,ROHS,FBGA2397 1SG280HU2F50E1VG IC,FPGA,STRATIX 10GX,2800K LE,96 XCVRS,H-TILE,ET,FBGA2397,ROHS 1SG280LU3F50I3YG IC,FPGA,STRATIX 10GX,L-TILE,2.8M LES,96 XCVRS,SCREENED STATIC PWR,50X50MM FBGA2397,ROHS PL-USB2-BLASTER CABLE ASSY,FPGA PROGRAMMING,USB-BLASTER II,FOR ALTERA DEVICES PL-USB-BLASTER-RCN DOWNLOAD CABLE,USB-BLASTER,INTEL FPGA,ROHS 10AS022C3U19I2LPAA IC,FPGA,ARRIA10 SX,SOC,6 XCVRS,220K LE,IT,LOW-PWR SCREENED,SNPB,UBGA484 10AX032H2F34I2LPAA IC,FPGA,ARRIA10 GX,24 XCVRS,320K LE,IT,LOW PWR SCREENED,SNPB,FBGA1152
MAX V Board test system: No USB Blaster detected
I am brand new to Altera stuff so I got the Max V dev kit and I am going to start learning but I have a snag here. It says No USB Blaster detected, even though I installed the driver and its right there in the device manager. Here's pic http://www.alteraforum.com/forum/attachment.php?attachmentid=12146&stc=1 Also is there a really really basic 'getting started guide for max V', like how to open a max V dev kit example design in Quartus and compile/upload it to the max V dev kit (with links to the example code and explain which version of Quartus because there are MANY)? The Altera ecosystem is very daunting for a person coming from TI and Xilinx. I need baby steps.Max1000 Remote System Upgrade via SPI
Hello, I have a Max1000 development board and would like to perform a remote system upgrade with it. I have programmed an SPI interface to send the required data. (Here not necessarily SPI must be used, but I think another interface does not change my problem). Now I want to program the RSU without the Nios. I have gotten to the point where I need the dual boot ip core to configure the "dual compressed image". An onchip-Ram to store the necessary data and an onchip-Flash to write to the CFM. But here my flash has only an address size of 17 bits, but to rewrite the CFM the address must be at least 18 bits. Am I missing something here? Is it possible to rewrite the CFM with SPI like this?SDRAM + I2C (nios II?) + VHDL + VGA= QSYS? Connecting VHDL with Qsys (DE0-Nano)
Hello, I need to control my camera OV7670 with I2C protocol (so it's best to use nios II i think) and i need to interface it with VGA and some image processing VHDL files, which will be fetching image from SDRAM (32 MB ISSI sdram) after it will be loaded there from camera (1. load image to sdram from camera though VHDL code, 2. process image to another place in SDRAM memory, 3. output processed file to VGA and mayby PC). Is it possible to somehow connect VHDL files (.vhd) with Qsys? Is this the best way for my project or should i choose another approach? I am asking You, because i dont want to do redundant work that will lead me to nowhere mayby...
JTAG error device not detected
Hello, I have a custom Arria10 board. I tested the power sequence and it looks good, I used the same chip LTC2924CGN#PBF as a reference design. I monitored with the oscilloscope the nCONFIG and nSTATUS and they go high after the last power rail (1.8V) has been turned on. I attached a section of a schematic with a JTAG connector and a mux and a voltage translator to program the Arria10. The default configuration of this setup is to program directly the Arria10. I am using the USB blaster (RevB) from Terasic. I also added the TCK signal measured at the connector, then after the mux-voltage translator and the TDO signal at the voltage translator chip. Any suggestion/idea would be highly appreciated.
I'm in trouble managing by the fpga section some pins connected to the hps section.
I have two input pin as buttons connected to hps and their status are the input to a component in fpga, they work correctly. The others 3 output pins, connected to hps as leds, are controlled by a component of the fpga managed by a NIOS routine, they doesn't work. I manage the leds by a custom component programmed by Avalon Memory Mapped Interface, its output is the status of single led ( off, on, slow blinking, fast blinking and so on) They stay permanently in ON state, independently to the the status programmed by software. in the attach, I have extracted the vhdl code of relative to the connection of the leds (not work) and the keys (working).Data from FPGA to host
Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this (http://www.alteraforum.com/forum/showthread.php?t=32354) and there's instructive information but it's a bit old and maybe there exist other ways. I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? Thanks for your help.
