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DE2-115 Nios VGA demo
Hi , I am trying to run an VGA demo on DE2-115 board , i followed this document attached which is final univ project(see attached). But after successfully generating and compiling Quartus ver 18.1 project and then its related software in Nios-ll Eclipse IDE i get this error "Downloading ELF Process Failed. See Quartus Project attached. Thanks, Regards
Help needed to start PAM4 loopback test on Stratix 10TX-SI Kit
Hi everyone, I am working with the Stratix 10 TX Transceiver Signal Integrity Development Kit and I am trying to run the PAM4 loopback test. I have followed the documentation and found both qts_pam4_com and bts_pam4.sof. I’m currently in Quartus with the bts_config project open, but I’m stuck on how to proceed to the BTS main page → PAM4 tab. Could someone please clarify the correct sequence for: bts_pam4.sof → FPGA configuration → launch qts_pam4_com/BTS → PAM4 tab → start QSFP-DD/2.4-mm loopback test? Do I need to compile bts_config, or can I directly use bts_pam4.sof? Any guidance would be greatly appreciated. Thanks! Kind,Board Test System Download Package – Stratix 10 TX Signal Integrity Development Kit
Hello, I am currently working with the Stratix 10 TX Signal Integrity Development Kit on a Windows PC and would like to use the Board Test System (BTS) to verify the functionality of the board. According to the Stratix 10 TX Transceiver Signal Integrity Development Kit User Guide, the BTS application should be included in the development kit package under: <package_dir>\examples\board_test_system\BoardTestSystem.exe However, I have not been able to locate the appropriate BTS package or download containing the BoardTestSystem.exe application. Could someone from Altera please provide the current download link or the appropriate installer/ZIP package containing the BTS application and its associated test designs (.sof files)? I would also appreciate confirmation of the recommended Quartus Prime version and any required dependencies for running the BTS on Windows. Board: Stratix 10 TX Signal Integrity Development Kit Development Kit: DKSI1STXEA Host OS: Windows Thank you for your assistance.
Workaround for TCK frq. limitations on USB-Blaster I/II/III & Clones (fixing "JTAG chain broken")
Workaround for TCK frequency limitations on USB-Blaster I/II/III and clones (fixing "JTAG chain broken") Hi everyone, I'd like to share a practical workaround for a problem many of us run into when programming Altera FPGAs through test fixtures, level shifters or long ribbon cables. **The problem** In these setups, "JTAG chain broken" or "Unable to scan device chain" errors are common. They are usually caused by signal reflections and poor termination on custom boards and long extensions. Lowering the TCK frequency is the standard remedy, but the options are limited: - USB-Blaster I (and most low-cost clones) runs at a fixed TCK of about 6 MHz. Quartus offers no way to change it. - USB-Blaster II can be set to 6/16/24 MHz via `jtagconfig --setparam <cable> JtagClock <freq>`, but nothing below 6 MHz. In practice this setting is also unreliable: it is not persistent and can fall back to the 24 MHz default (see Altera KB: "Why does the TCK frequency setting of the USB-Blaster II download cable revert to the default value of 24 MHz after being changed?"). In our experience it is a constant source of trouble, especially in production where it has to be set again and again. For really marginal lines, 6 MHz is often still too fast. **The workaround** Disclosure: I'm the developer of the tool described below, so please take this as information from the vendor. Quintus Programmer (by Dution) drives the JTAG lines of the USB-Blaster in bit-bang mode instead of using the adapter's fixed shift clock. This lets you choose the TCK frequency freely, e.g. down to 100 kHz, with the same USB-Blaster I/II/III or clones you already have. With a lower TCK, programming and verification become stable again on long or poorly terminated lines without any hardware changes. The standard USB-Blaster driver stays in place, and Quintus only replaces the programming step. **Before reaching for software, check the hardware basics** The recommendations from the Altera Knowledge Base still apply and often fix the problem on their own: - TCK pull-down 1 kΩ to GND, TMS/TDI pull-up 10 kΩ to VCCIO - a small capacitor (10–22 pF) at TCK near the FPGA against ringing edges - a TCK buffer on long or noisy lines If the layout can't be changed, a lower TCK is a practical way out. More info: search for "Quintus Programmer Dution". Happy to answer technical questions here.Rev B Arria 10 development kit
Rev A / Power Solution 1 DK-DEV-10AX115S-A Product page: https://www.altera.com/products/devkit/po-3017/arria-10-gx-fpga-development-kit Rev B / Power Solution 2 DK-DEV-10AX115S-B Product page: https://www.altera.com/products/devkit/po-3320/arria-10-gx-fpga-development-kit We are looking early into Rev B version of Arria 10 dev.kit. I can't found any BOM yet, and I would like to know if flash components were changed? At least EPQCL flash is inconveniently under heat sink and fans. I would like not to replace thermal compound.
Agilex 5 E-Series 065B Premium Dev Kit - is FPGA_3V3_SDA/SCL driven by an HPS I2C controller?
Board: Agilex 5 E-Series 065B Premium Dev Kit (A5ED065BB32A) In the schematic, FPGA_3V3_SDA/SCL (U402 MAC EEPROM at 0x56/0x5E, QSFP1/2 at 0x50) goes to Bank 5A HVIO pins (page 17), not to the dedicated HPS_IOA/IOB I2C pins (page 12). So my understanding is that an HPS I2C controller can drive this bus only if it is routed to the FPGA fabric in the HPS IP, or if a soft I2C master drives it. Questions: 1. Is that correct, and does the kit's reference design connect an HPS I2C or a soft I2C IP to these pins? 2. How do I confirm which controller drives these pins in Quartus Prime software and at runtime in Linux? Thanks,Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Design of MAX V CPLD 5M2210 System Controller in Arria 10 SoC board
Hi Altera, Could you help to share the MAX V CPLD 5M2210 System Controller with me? We're in AI research work with Arria 10 SoC board and need the source code of system maxV but is not included in the installer package, arria10_10as066n3f40_soc_v15.1.2.zip. Thank you!