Recent Discussions
nCONFIG and nSTATUS,CONF_DONE always LOW EP4CE6
Hello everyone, i has problem about hardware of EP4CE6E22C8, i configure initialize pin like under About power supply, i sure that every bank has right voltage. The problem is when i connected through USB Blaster, quartus cannot detect device, when measure initialize pin, i see voltage in nSTATUS, nCONFIG, CONF_DONE always 0V although 3v3 pull up work. I checked chip solder right, 3v3 work, nSTATUS, nCONFIG, CONF_DONE do not touch GND. What should i do next ? Thanks everyone.
Flash Loader IP not loaded on device 1?
Hello, I have a Cyclone IV based FPGA board (LimeSDR-PCIe v1.3) I am trying to flash FPGA FW but in Quartus I always get this error. "Flash loader IP not loaded on device 1" see log below. /altera_lite/15.1/quartus/bin$ quartus_pgm -m jtag -o "ipv;./LimeSDR-PCIE_lms7_trx_HW_1.3.jic" Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 15.1.2 Build 193 02/01/2016 SJ Lite Edition Info: Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera MegaCore Function License Agreement, or other Info: applicable license agreement, including, without limitation, Info: that your use is for the sole purpose of programming logic Info: devices manufactured by Altera and sold by Altera or its Info: authorized distributors. Please refer to the applicable Info: agreement for further details. Info: Processing started: Wed Apr 22 13:06:06 2020 Info: Command: quartus_pgm -m jtag -o ipv;./LimeSDR-PCIE_lms7_trx_HW_1.3.jic Info (213045): Using programming cable "USB-Blaster [1-2]" Info (213011): Using programming file ./LimeSDR-PCIE_lms7_trx_HW_1.3.jic with checksum 0x7273C3BF for device EP4CGX30CF23@1 Info (209060): Started Programmer operation at Wed Apr 22 13:06:07 2020 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x028230DD Info (209007): Configuration succeeded -- 1 device(s) configured Error (209062): Flash Loader IP not loaded on device 1 Error (209012): Operation failed Info (209061): Ended Programmer operation at Wed Apr 22 13:06:11 2020 Error: Quartus Prime Programmer was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 411 megabytes Error: Processing ended: Wed Apr 22 13:06:11 2020 Error: Elapsed time: 00:00:05 Error: Total CPU time (on all processors): 00:00:01 Can anyone guide me what the issue could be, Is there some file missing? The repo is available here: https://github.com/myriadrf/LimeSDR-PCIe_GW I am using Quartus Lite 15.1.2 Build 193. Thanks.
DE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? Thanks
Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue
The FMC VCC IO voltage level is adjustable using a resistor on the board as shown below. The default is 1.8V and that works fine. When I depopulate the resistor (R468) to get 1.2V, the output voltage goes to 0V and the enable line for the DC-DC converter also goes low. Any idea what the reason for this is? And what is the fix?MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry H
Ubuntu 18 LXDE image for DE10 Nano board
Hello, I wanted to install CUPS in Linux running on HPS side of DE10 Nano, but the current version of Ubunto is 16.04 in LXDE image that comes with it. THat version has reached to EOL, so I was wondering if I could find LXDE image with Ubuntu 18 and could easily install CUPS on it via APT update. Thanks in advance
Does the FPGA N3000 support OpenCL and OneApi?
I received an INTEL FPGA PAC N3000 card, and taking the opportunity, I decided to learn how to develop with SYCL and oneAPI. However, I ran into problems. I fully installed the FPGA PAC N3000 Acceleration Stacks v1.3.1 and also updated the board's BMC from D.1.0.12 to D.2.0.19. Then I started configuring oneAPI 2022 using intel-basekit and fpga-addon, but proper configuration requires bsp, and I couldn't find it anywhere. I also saw that on the website page for Quartus Prime Pro 19.2, which is installed with IAS 1.3.1, there's a tab with oneAPI and BSPs for boards. I looked at other versions, but I only found mentions of Arria 10-GX and Arria 10-SX. I'm not sure if this will help, but the log is from CentOS 7.6.1810. [root@node-fpga ~]# fpgainfo fme Board Management Controller, MAX10 NIOS FW version D.2.0.19 Board Management Controller, MAX10 Build version D.2.0.6 //****** FME ******// Object Id : 0xF300000 PCIe s:b:d.f : 0000:84:00.0 Device Id : 0x0b30 Numa Node : 1 Ports Num : 01 Bitstream Id : 0x23000110010309 Bitstream Version : 0.2.3 Pr Interface Id : f3c99413-5081-4aad-bced-07eb84a6d0bb Boot Page : user [root@node-fpga ~]# fpgainfo bmc Board Management Controller, MAX10 NIOS FW version D.2.0.19 Board Management Controller, MAX10 Build version D.2.0.6 //****** BMC SENSORS ******// Object Id : 0xF300000 PCIe s:b:d.f : 0000:84:00.0 Device Id : 0x0b30 Numa Node : 1 Ports Num : 01 Bitstream Id : 0x23000110010309 Bitstream Version : 0.2.3 Pr Interface Id : f3c99413-5081-4aad-bced-07eb84a6d0bb ( 1) Board Power : 59.65 Watts ( 2) 12V Backplane Current : 2.91 Amps ( 3) 12V Backplane Voltage : 11.92 Volts ( 4) 1.2V Voltage : 1.20 Volts ( 6) 1.8V Voltage : 1.80 Volts ( 8) 3.3V Voltage : 3.27 Volts (10) FPGA Core Voltage : 0.90 Volts (11) FPGA Core Current : 14.47 Amps (12) FPGA Core Temperature : 62.50 Celsius (13) Board Temperature : 42.00 Celsius (14) QSFP A Voltage : N/A (15) QSFP A Temperature : N/A (24) 12V AUX Current : 2.08 Amps (25) 12V AUX Voltage : 11.97 Volts (37) QSFP B Voltage : N/A (38) QSFP B Temperature : N/A (44) Retimer A Core Temperature : 63.00 Celsius (45) Retimer A Serdes Temperature : 64.00 Celsius (46) Retimer B Core Temperature : 0.00 Celsius (47) Retimer B Serdes Temperature : 0.00 Celsius [root@node-fpga ~]# aoc -list-boards Board list: pac_a10 (default) Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac pac_s10 Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_s10sx_pac pac_s10_usm Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_s10sx_pac Memories: device, host [root@node-fpga ~]# aocl list-devices -------------------------------------------------------------------- Device Name: acl0 BSP Install Location: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac Vendor: Intel Corp Physical Dev Name Status Information pac_f200000 Uninitialized OpenCL BSP not loaded. Must load BSP using command: 'aocl program <device_name> <aocx_file>' before running OpenCL programs using this device DIAGNOSTIC_PASSED -------------------------------------------------------------------- [root@node-fpga ~]# aocl initialize acl0 pac_a10 aocl initialize: Running initialize from /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac/linux64/libexec bitstream.c:391:validate_bitstream_metadata() **ERROR** : Interface ID check failed Error writing bitstream to FPGA: invalid parameter Error programming device aocl initialize: Program failed. [root@node-fpga ~]#About old Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
I can see that the old version of Quartus has come back, so I will give it a chance. Could Altera offical upload the "SIIGX_SI_Kit-v1.0.1.exe" file again for "Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board"? Any help would be appreciated.