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DK-DEV-AGI027RBES missing device selection
Hi, Saw similar issues on slightly different part numbers. I have the following ES2 development board: DK-DEV-AGI027RBES which has the AGIB027R29A1E2VR3 device part number. I couldn't find this part number in Quartus Pro 26.1 nor older versions like Quartus Pro 23.3 Furthermore, when running JTAG scan in 23.3 it seems like IDCODE is shared across multiple devices where neither of them is the part I have: Quartus 23.3 device selection does show the part I have: I prefer working with 26.1 and receiving a patch to support this part number if possible, if not please guide which Quartus version is best to use in my case. Thanks!
in MAX 10 Dev kit
Hi Altera Community, I am encountering a JTAG Server Error Code 35 when attempting to program my MAX 10 Development Kit using the USB-Blaster. Below are the details of my setup and the issue: Board: MAX 10 Development Kit Programmer Cable: USB-Blaster Problem Description: When opening the Quartus Programmer and clicking Start (or running Auto Detect), the process fails with the following log: Error (209053): Unexpected error in JTAG server -- error code 35 Error (209040): Can't access JTAG chain
Cyclone® 10 GX FPGA Development Kit (Version B) DK-DEV-10CX220-B Installer Package (v22.4 or higher)
Good morning, I'm trying to donwload the Installer package for DK-DEV-10CX220-A and or B from altera website, but i'm getting always error 502. https://docs.altera.com/v/u/resources/649830/cyclone-10-gx-fpga-development-kit-version-a-dk-dev-10cx220-installer-package-v22.4-or-higher https://docs.altera.com/v/u/resources/838158/cyclone-10-gx-fpga-development-kit-version-b-dk-dev-10cx220-b-installer-package-v22.4-or-higher I tried from Windows, linux and with different PCs but is always the same, so assume the Server is down or the installation file has been remove. Can someone please reuplaod it for me? Thanks Xavier Ruiz
Agilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)
Device: A5ED013BB32AE4SCS Quartus Prime Pro 25.1.1 Build 125 I am trying to reconfigure a standalone fabric IOPLL at runtime using the EMIF Calibration IP (emif_io96b_cal), following the HSIO reconfiguration flow described in the Clocking and PLL User Guide (813671), section 6.1/6.4, and the approach discussed in this thread: Agilex 5 reconfigurable PLL - emif | Altera Community - 122952 Setup: - ps_pll: Intel IOPLL FPGA IP, "Enable dynamic reconfiguration of PLL using Calibration IP" = true, IOPLL Type = "I/O Bank" (only selectable value in the GUI), 50 MHz reference clock. - EMIF Calibration IP (emif_io96b_cal), INSTANCE_ID = 0, NUM_CALBUS_PLLS = 1, NUM_CALBUS_PERIPHS = 0, AXI4-Lite subordinate port in FABRIC mode. - pll_calbus / pll_calbus_readdata wired directly between the two IPs. The Fitter fails during the very first placement/plan stage with: Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Error(175001): The Fitter cannot place 1 IOPLL, which is within IOPLL FPGA IP ps_pll_altera_iopll_2000_ihvozry. Error(16234): No legal location could be found out of 11 considered location(s). Error(175005): Could not find a location with: HVIO_IOPLL (6 locations affected) Error(175008): Location was not in the legal region (5 locations affected) I isolated this down to a minimal reproduction: 1) A plain, non-reconfigurable IOPLL alone: places fine. 2) The same IOPLL with calbus reconfiguration enabled, standalone (no EMIF IP at all): places fine. 3) The EMIF Calibration IP alone, calbus tied off, unconnected to any PLL: places fine. 4) The reconfigurable IOPLL and EMIF Calibration IP both present in the same design but NOT wired together (calbus tied off independently on each side): places fine. 5) The reconfigurable IOPLL wired to the EMIF Calibration IP via calbus (the actual intended configuration): fails with the error above, 100% reproducible, regardless of I/O pin location assignments (confirmed by removing every pin constraint from the design entirely - identical error, identical 6+5 location breakdown). I have also tried, with no change to the error: - Removing all pin location assignments (refclk, PLL outputs, etc.) - Setting PLL_REFCLK_INPUT_TYPE to NOT_BALANCED on the IOPLL instance - Quartus Interface Planner tool - "Update Plan" fails immediately with the identical underlying Fitter conflict, before it can even display a plan. Can someone from Intel/Altera help me understand what is actually driving this placement conflict and how to resolve it? Happy to share the minimal reproduction project if useful.
Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera
Hi, This is regarding the clock tree used in the Agilex 7 FPGA M-Series Development Kit. I have a few questions and would appreciate your clarification. 1. Why is the 390.625 MHz SyncE clock generated by the Si5518 (U92) provided to the Si5395 (U14) and subsequently routed through the Si5391 devices to the DDR5 and HBM reference clock pins of the Agilex M FPGA? 2. Why is the output of Si5391 (U35) connected to an input of another Si5391 (U93), and similarly, why is an output of U93 connected back to an input of U35? What is the purpose of these interconnections? 3. Why is the 312.5 MHz LVDS SAMPLE clock output from the Si5518 connected to the ToD block of the Agilex M FPGA? What function does this signal serve in the ToD block? 4. In the Si5518, why is the PPS output looped back to one of the PLL inputs (1PPSFB)? What is the purpose of this feedback connection in the schematic? 5. Similar loopback connections are also observed in Bank 13C of the Agilex M FPGA. Why is this loopback connection required ? I would appreciate your response to these queries. Any pointers to relevant documentation or application notes would also be very helpful Regards, ThulasiSyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design
Hi, In Agilex 7 M-Series Evaluation Kit clock tree, the 390.625 MHz SyncE (Synchronous Ethernet) recovered/reference clock is distributed through the Si5395/Si5391 clock generators and is used to generate clocks for the DDR5, HBM, and FPGA control/SDM interfaces. My understanding is that a recovered SyncE clock is primarily intended for Ethernet frequency synchronization. Therefore, I am trying to understand the design rationale behind using it as the master reference for non-Ethernet interfaces on the board. Could someone please clarify: Why is the SyncE clock chosen as the primary reference for generating DDR5, HBM, and FPGA control interface clocks? What are the advantages of using the SyncE reference instead of a dedicated crystal oscillator or another fixed-frequency reference? Is this done to maintain frequency synchronization across the entire system, or are there other design considerations such as clock quality, jitter performance, or timing alignment? Is this approach recommended only for the evaluation board, or is it also the recommended clocking architecture for custom Agilex M-Series designs? Any explanation or reference to the relevant Intel documentation would be greatly appreciated. Thank you.Why 390.625MHz clock to F-Tile Reference fequency
Hi, This question is regarding the Agilex 7 M-Series FPGA Development Kit. In the evaluation board schematics, the Si5518 provides a 390.625 MHz clock that is connected to two F-Tile reference clock inputs. From the F-Tile Ethernet Hard IP User Guide, I understand that standard Ethernet designs typically use 156.25 MHz as the PMA reference clock, while the 390.625 MHz clock appears internally as the clk_txmac/clk_rxmac clock. My questions are: 1. Which F-Tile configuration or interface is intended to use the external 390.625 MHz reference clock on the development board? 2. Is this reference intended for the Ethernet Hard IP, PMA Direct mode, SyncE, or some other transceiver application? 3. Are there any official reference designs that use this 390.625 MHz reference clock? I would appreciate it if you could clarify the intended use of this clock on the Agilex M Development Kit. Regards,
