Recent Discussions
Cyclone VGT Dev Kit boards - some new boards failing to boot from NOR Flash
We've been using these boards for years, having certified them for use in one of our products. In the last few months we have now received 5 of these boards and they fail to configure from NOR flash. These are all the new Rev B CVGT Dev Kit edition. Not all of the new RevB fail, but the fail rate is high, getting close to 50%. Yes, we know they changed to a Micron NOR flash for Rev B and rerouted some data lines, we are using the new RevB MAX5 files and have updated the Cyclone V NOR flash pins to match as well. I made some diagnostic changes to the MAX5 boot source (I set the PGM leds to count retries) and discovered that on the bad boards, the boot process goes through multiple configuration retries and eventually the watchdog timer fires, turns on the ERR (D5) red LED and stops. With the factory image they come with, there are also dozens of retries, then sometimes the boards fail, sometimes they boot up. With the slow speed that the NOR flash configuration runs at, there is no reason that it should ever fail and retry, and indeed on good boards they configure the first time every time with no retries. The first four we were able to send back to Altera (Via digikey where we bought them). We just got another bad one yesterday, this one from Mouser. Has anyone else seen this issue, and/or heard from Altera about this? Board link: https://docs.altera.com/r/docs/792833/current/cyclone-v-gt-fpga-development-kit-user-guide/kit-features
JTAG pins order for USB Blaster III - 1.27" header
USB Blaster III header has shrined in size relatively to the previous JTAG cables. I see that in addition, pinout order has changed(according to USB Blaster III user guide). So, if I want to place on a new board that I'm developing a matching connector(pitch=1.27") for USB Blaster III (without using the adapter board from the KIT), then I have to use new pinout order: 1-VCC_TRGET, 2-TMS, 3-GND, 4-TCK, 6-TDO, 7-nTRST, 8-TDI, 9-GND, 10-nPROCRST. This order is different then was used with previous JTAG cables. I couldn't find any reference schematic(also of EVAL KITs) that supports this new JTAG order. I will appreciate if anyone from the forum can confirm my observation. If it's possible that someone can answer me with an existing working reference design with 1.27" connector, I will appreciate it more.Request for SmartVID PMBus Compatibility Requirements for Replacing VRM on Agilex 7
Dear Altera Support Team, We are designing a board using Agilex 7 AGMA032R47A1E2VC and currently plan to use Infineon XDPE19284C as the SmartVID voltage regulator. Due to cost and design complexity considerations, we are evaluating replacing the XDPE19284C with a TI solution, such as TPS546E25 (multi-device stack configuration). Our goal is to make the VRM replacement transparent to the Agilex SDM SmartVID function. In other words, after replacement, the Agilex device should operate normally without any changes in the SmartVID behavior. We understand that SmartVID communicates with the external VRM through PMBus, and that Agilex SDM does not depend on the internal VRM implementation (such as phase number). However, we would like to confirm all the required compatibility conditions. Could you please provide a complete checklist of the PMBus parameters and behaviors that must be identical between the original VRM and the replacement VRM? For example, we would like to confirm whether the following items are required to match: 1.PMBus slave address 2.VOUT_MODE (PMBus command 0x20) 3.Linear format exponent (N value) 4.VOUT_COMMAND format and scaling 5.READ_VOUT response format 6.OPERATION command behavior 7.STATUS_WORD / STATUS_BYTE behavior 8.PAGE command support and configuration 9.PMBus bus speed requirement 10.Any required Manufacturer Specific Commands (MFR_xxxx) 11.Any other SDM-specific PMBus transactions used during SmartVID initialization In particular, we would like to know: Does Agilex SDM SmartVID use only standard PMBus commands (such as VOUT_COMMAND, READ_VOUT, STATUS_WORD, OPERATION)? Does Agilex SDM access any VRM-specific Manufacturer Commands? Does Agilex identify or depend on the specific VRM model selected in Quartus? If the Quartus setting is configured as "Other" VRM, what exact requirements must the replacement regulator satisfy? Our understanding is that the most critical parameters for a Linear PMBus regulator are: PMBus address VOUT_MODE Linear format Linear exponent N VOUT_COMMAND interpretation However, we would like to confirm this with Altera before committing to a new PCB design. Could you please provide a detailed compatibility checklist or any internal guideline/documentation regarding SmartVID VRM replacement? Thank you very much for your support. Best regards,
ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
Hi Team, We recently purchased license for the ARM DS5 IDE from Altera with License file contains note as NOTICE="For use with Intel or Altera devices only". I am using Arm Development studio IDE with version 2025.1-1. ALtera Agilex 5 FPGA device configured with custom soft macro based design which is only having ARM Cortex M55 processor cores with coresight debug IP . My question is whether ARM DS IDE will detect, access and debug the Cortex M55 cores which is in the fpga through the JTAG USB Blaster ? Please provide the detailed explanation Regards SureshDE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? ThanksIs it possible to attach PCIe to a Dev kit?
Hello Altera Community I have the DE25 Nano dev kit from Terasic. The Altera Agilex 5 product breif says the this FPGA has PCIe, but on the Dev kit this have not been installed. The pins for this should be exposed right? Is it possible that I could attach a PCIe component myself and how would that be possible? Thanks in advance.Why 390.625MHz clock to F-Tile Reference fequency
Hi, This question is regarding the Agilex 7 M-Series FPGA Development Kit. In the evaluation board schematics, the Si5518 provides a 390.625 MHz clock that is connected to two F-Tile reference clock inputs. From the F-Tile Ethernet Hard IP User Guide, I understand that standard Ethernet designs typically use 156.25 MHz as the PMA reference clock, while the 390.625 MHz clock appears internally as the clk_txmac/clk_rxmac clock. My questions are: 1. Which F-Tile configuration or interface is intended to use the external 390.625 MHz reference clock on the development board? 2. Is this reference intended for the Ethernet Hard IP, PMA Direct mode, SyncE, or some other transceiver application? 3. Are there any official reference designs that use this 390.625 MHz reference clock? I would appreciate it if you could clarify the intended use of this clock on the Agilex M Development Kit. Regards,Stratix III FPGA development kit
Hello! I am currently facing an unusual issue when trying to use the Stratix III FPGA Development Kit. After installing Quartus II 13.1 Subscription Edition (the last version supporting the Stratix III family) along with the respective device files (.qdz) for Cyclone, Arria, and Stratix III, and properly configuring the license on Windows 11, the Stratix III family does not appear in the device selection wizard. Interestingly, the Quartus Device Installer states that the family is already installed, but it remains hidden inside the software. To isolate the issue, I have tested multiple operating systems and Quartus versions, but the problem persists: 1) Windows 11 & Windows 7 (Quartus II 13.1, 13.0, and 12.1 Subscription): Arria and Cyclone families work perfectly. Stratix III shows as installed in the device manager but is unavailable inside Quartus. 2) Windows 7 (Quartus II 9.0 Web Edition): The Stratix III family appears in the family selection menu in Quartus, but our specific device (EP3SL150F1152) is listed as unsupported. 3) Ubuntu 12.04 (Quartus II 13.1 Subscription): Same behavior as Windows; the installer claims it is there, but Quartus does not show it. Given these cross-platform results, I suspect the root cause might be: 1) A corrupted or flawed Stratix III device installer file (.qdz). 2) A licensing restriction, where our current license might need a specific feature enabled for the Stratix III family, even though the software allows the installation. I have already tried renaming the device installation file, but the Quartus 13.1 device installer does not accept any name other than "stratixiv-13.1.0.162.qdz". When I use this default name, a window appears with the checkboxes ticked for the Stratix III family (indicating it is already installed). I cannot uncheck these boxes to uninstall only this specific family. I was also careful to place the .qdz file inside a folder with a simple name—without spaces or special characters—as I am aware of this classic Quartus 13.1 bug. Even so, nothing seems to solve the problem, and I am truly at a loss as to what might be going wrong. I am happy to make my machine available for you to take a closer look at the issue using TeamViewer, AnyDesk, or any other remote access tool. Could you please guide me on how to get this Stratix III Development Kit operational (which features the EP3SL150F1152 device)?" Thank you for your time and assistance. I look forward to your guidance. Best regards!Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera
Hi, This is regarding the clock tree used in the Agilex 7 FPGA M-Series Development Kit. I have a few questions and would appreciate your clarification. 1. Why is the 390.625 MHz SyncE clock generated by the Si5518 (U92) provided to the Si5395 (U14) and subsequently routed through the Si5391 devices to the DDR5 and HBM reference clock pins of the Agilex M FPGA? 2. Why is the output of Si5391 (U35) connected to an input of another Si5391 (U93), and similarly, why is an output of U93 connected back to an input of U35? What is the purpose of these interconnections? 3. Why is the 312.5 MHz LVDS SAMPLE clock output from the Si5518 connected to the ToD block of the Agilex M FPGA? What function does this signal serve in the ToD block? 4. In the Si5518, why is the PPS output looped back to one of the PLL inputs (1PPSFB)? What is the purpose of this feedback connection in the schematic? 5. Similar loopback connections are also observed in Bank 13C of the Agilex M FPGA. Why is this loopback connection required ? I would appreciate your response to these queries. Any pointers to relevant documentation or application notes would also be very helpful Regards, Thulasi
