PCIe Example Design for Arrow EAGLE Board
Hello !! I'm using Arrow Agilex-5 EAGLE Board with Device A5ED065BB32AE4SR0 with Q25.1 I've generated IP Core Example Design for Development Kit selected NONE. GTS AXI Streaming Intel FPGA IP for PCI Express Then, I've compiled the Example Design and then modified the pins to match the Agilex-5 EAGLE Board schematics. There are several problems: - input p0_pin_perst_n_i_reset_n assigned to PIN_CF132 which is PCIE_RTSb - input p0_pin_perst_n_1_i_reset_n I've tried to assign to many different pins which were reasonable to connect, but was getting error during the Fitting stage. The only pin assignment which passing compilation is suggested by tool: PIN_BU109 which is according to schematics CX_SMB_SDA - input refclk_clk I had to connect to PIN_A23 which is FPGA_25M_CLK and thus I had to change IO PLL Reference Clock to 25MHz instead of default 100MHz After design was successfully compiled, it was programmed to Agilex-5 FPGA and connected to PC running Ubuntu 24.04.2 LTS. Then, I've tried to list PCIe devices with command lspci and I never got Altera Agilex-5 device recognized between PCIe devices. So, now, I'm not sure, if the problem with pin assignment or something else. Does anyone tried PCIe IP for EAGLE Board or probably someone can assist??? Thanks in advice!!!
Agilex5 Eagle ES, NIOS-V + TSE IP
Trying to setup a NIOS-V with a TSE MAC to utilize the ethernet interface connected to the FPGA on the Agilex Eagle ES devkit. NIOS executes firmware and able to read the PHY registers. But when connecting the ethernet cable nothing seems to happen, status registers does not change and no link-up is reported. Does anyone know of any examples using the NIOS-V and TSE with RGMII interface that I can look at to troubleshoot the issue ?
Device stopped receiving config data: Internal error (0x0000, 0x00000000, 0x1800).
Using Agilex AGFB014R24A (E-Tile board). .jic flashes successfully, but no UART logs are observed after boot. Observed attached logs attached When programming the corresponding .sof via JTAG, configuration fails at ~86%. Device has stopped receiving configuration data Error message received from device: Internal error. (Subcode 0x0000, Info 0x00000000, Location 0x00001800) Operation failed Ended Programmer operation Looking for clarification on this internal error and recommended workaround.
Slow Runtime Performance in FIL Implementation on DE2-115 Using Ethernet
Dear Technical Support Team, I am currently working on an FPGA-in-the-Loop (FIL) implementation using the DE2-115 FPGA development board with MATLAB/Simulink. My objective is to implement a complete PMSM drive system in FIL, which includes: A three-phase PWM inverter model A Permanent Magnet Synchronous Machine (PMSM) model The system is developed in Simulink, converted to HDL, and deployed to the DE2-115 board using HDL Verifier. The FIL setup is functioning correctly, and communication with the FPGA board through Ethernet is established successfully. The FPGA bitstream is generated and loaded without issues. However, during FIL simulation I observe that the runtime execution is very slow compared to the expected performance, and the simulation progresses significantly slower than real time. I would like to ask whether this behavior is expected when implementing a full electrical drive system inside the FIL environment. From reviewing several publications, it appears that many implementations only place a portion of the drive system in the FPGA. For example: * Bogdan Fabiański, “FPGA Emulator of Switched Reluctance Motor in a FIL Structure,” Poznan University of Technology Academic Journals, Electrical Engineering, No. 87, 2016. * Ahmet Gundogdu, Resat Celikel, Beşir Dandil, and F. Ata, “FPGA-in-the-loop implementation of direct torque control for induction motor,” Automatika, 2021, DOI: 10.1080/00051144.2021.1934365. In these works, only specific parts of the system (such as the motor model or control algorithm) are implemented on the FPGA, while the remaining components remain in the simulation environment. Therefore, I would appreciate your guidance on the following points: 1. Is it recommended to implement the entire drive system (inverter and machine model) inside the FIL for the DE2-115 platform? 2. Are there known performance limitations when using Ethernet-based FIL communication for relatively large models? 3. Is there a recommended partitioning strategy between the FPGA and Simulink for electric drive simulations? If necessary, I can provide the model configuration, HDL Workflow Advisor settings, or additional implementation details. Thank you for your support. Kind regards, Ahmed Sayed SolimanMandelbrot viewer on Cyclone V - Platform Designer layout
Hello, I’ve been trying to implement on my DE1-SoC an outstanding Mandelbrot Viewer written by 3 fellows at Cornell, which published partial information in an online available final report I manage to compile the C++ code and perform a sanity check on my x86 host: And I manage to compile the C++ to run on the DE1-SoC HPS: Also, I got Quartus to compile the Verilog provided in the report, though it’s not in its final, working form. I’m pretty sure my problem is in the Platform Designer (formerly Qsys) layout. Been trying many variations around this layout for several weeks, but with no success: I chose the components to my best understanding based the report, that mentions: "The communication between the FPGA and the hard processor system happens over a memory-mapped AXI bus. Requests for tiles are placed into a FIFO on the FPGA, and solved tile data is written out into external SDRAM memory. Requests from the HPS are sent over the AXI bus into a FIFO located on the FPGA. A request distributor then pulls the message off of the FIFO using the avalon streaming interface and handles it. (I assume this is with reference to request_distributor.sv attached in report) As the solvers solve pixels of the output tile, they write the results to SDRAM. Arbitration logic collects results from any solvers which are ready to write. (I assume this is with reference to write_arbitrator.sv attached in report)" Additional info: To my understanding, a top module (not attached to the report) is probably instantiating a multi_tile_solver.sv module and a module from Platform Designer, nothing more. As can be seen in the files in the report, multi_tile_solver.sv instantiates a request_distributor.sv module, a write_arbitrator.sv module, and NUM_SOLVERS tile_solver_legit.sv modules. Each tile_solver_legit.sv instantiates a solver.v, which instantiates a solver_control.v and a solver_datapath.v. It uses on-chip SRAM in the form of M10K block, which are created from the verilog source code, rather than having anything to do with the Platform Designer layout. I think I’m pretty close to running this amazing project, yet have been stuck on this platform designer layout and don’t succeed in finalizing. Any help would be much appreciated.
Stratix 10 GX SI Board - issue with the Board Test System (BTS)
We recently purchased several Stratix 10 GX Signal Integrity development boards and would appreciate your advice regarding an issue with the Board Test System (BTS). When attempting to program the FPGA using the .sof files available under the Configure tab in BTS, none of the designs can be successfully programmed. The system consistently reports: “Detected bts_config.sof on FPGA.” It appears that the FPGA remains running the default bts_config.sof, and the selected configurations do not load as expected. This happens when the Quartus version in the QUARTUS_ROOTDIR is the Quartus standard. If I change it to Quartus Pro version ( I tried 22.1 24.1 and 25.1), the BTS will not be open, and it gets stuck at "Setup connection to System Console server". Could you please let us know whether this is a known issue and advise on how to resolve it? I think it might be related to the version of Quartus we use. If so, please can you suggest which latest version we should use for the BTS? Thank you very much for your assistance. Best regards, Toni771About PCIe Daughter Cards for Agilex™ 3 FPGA and SoC C‑Series Development Kit
Dear Support Team, I would like to ask for clarification regarding the PCIe add‑in cards for the Agilex™ 3 FPGA and SoC C‑Series Development Kit. In the User Guide, Table 5. Available PCIe Daughter Cards lists the following two models: 3.3. Modes of Operations • Agilex™ 3 FPGA and SoC C-Series Development Kit User Guide • Altera Documentation and Resources Center ・DC-A3PCIE ・DC-A3SOCPCIE Could you please provide documentation that explains the differences between these two daughter cards—such as their appearance, functionality, or any other technical distinctions? I have already downloaded the installer package for the development kit, but the documents folder was empty, and I could not find detailed information about these PCIe daughter cards. If there is a specific document, datasheet, or application note that describes these two cards in more detail, I would appreciate it if you could point me to the correct resource. Thank you very much for your support. Best regards, Gesso
