MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry H
About PCIe Daughter Cards for Agilex™ 3 FPGA and SoC C‑Series Development Kit
Dear Support Team, I would like to ask for clarification regarding the PCIe add‑in cards for the Agilex™ 3 FPGA and SoC C‑Series Development Kit. In the User Guide, Table 5. Available PCIe Daughter Cards lists the following two models: 3.3. Modes of Operations • Agilex™ 3 FPGA and SoC C-Series Development Kit User Guide • Altera Documentation and Resources Center ・DC-A3PCIE ・DC-A3SOCPCIE Could you please provide documentation that explains the differences between these two daughter cards—such as their appearance, functionality, or any other technical distinctions? I have already downloaded the installer package for the development kit, but the documents folder was empty, and I could not find detailed information about these PCIe daughter cards. If there is a specific document, datasheet, or application note that describes these two cards in more detail, I would appreciate it if you could point me to the correct resource. Thank you very much for your support. Best regards, Gesso
Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue
The FMC VCC IO voltage level is adjustable using a resistor on the board as shown below. The default is 1.8V and that works fine. When I depopulate the resistor (R468) to get 1.2V, the output voltage goes to 0V and the enable line for the DC-DC converter also goes low. Any idea what the reason for this is? And what is the fix?
Regarding Quartus Prime License Activation for the Agilex 5 Evaluation Kit
Does the Agilex 5 Premium Development Kit include a one‑year paid Quartus Prime license? The product brief states that it is included, but I would like to confirm. https://docs.altera.com/v/u/docs/815177/agilextm-5-fpga-e-series-065b-premium-fpga-development-kit-product-brief If the license is included: ・Is the same one‑year license also provided with the Modular Development Kit? ・Does the bundled license also include the IP Base Suite, as with a standard paid Quartus Prime license?
A question about reading the configuration space of the R-Tile PCIe IP EP
Hello, Recently, I generated an EP device using the R-Tile PCIe IP, and I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 as 0x002100B0, while the .xlsx file states it is 0x000800B0. Shouldn't the PCIe configuration space be 4KB? Why are 16-bit address lines being used to access the configuration space? Given that the read data width is 8 bits, does a value of a configuration register (32 bits) need to be read four times to be obtained? If I want to know the bus number and device number of the EP device in the user logic, can I directly obtain these from the configuration registers? Thank you! Recently, I generated an EP device using the R-Tile PCIe IP. I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 is 0x002100B0, while the .xlsx file states it is 0x000800B0. Additionally, shouldn’t the PCIe configuration space be 4KB? Why are 16-bit address lines used to access the configuration space? Furthermore, if I want to know the bus number and device number of the EP device in the user logic, can I directly obtain them from the configuration registers? Thank you!
Mandelbrot viewer on Cyclone V - Platform Designer layout
Hello, I’ve been trying to implement on my DE1-SoC an outstanding Mandelbrot Viewer written by 3 fellows at Cornell, which published partial information in an online available final report I manage to compile the C++ code and perform a sanity check on my x86 host: And I manage to compile the C++ to run on the DE1-SoC HPS: Also, I got Quartus to compile the Verilog provided in the report, though it’s not in its final, working form. I’m pretty sure my problem is in the Platform Designer (formerly Qsys) layout. Been trying many variations around this layout for several weeks, but with no success: I chose the components to my best understanding based the report, that mentions: "The communication between the FPGA and the hard processor system happens over a memory-mapped AXI bus. Requests for tiles are placed into a FIFO on the FPGA, and solved tile data is written out into external SDRAM memory. Requests from the HPS are sent over the AXI bus into a FIFO located on the FPGA. A request distributor then pulls the message off of the FIFO using the avalon streaming interface and handles it. (I assume this is with reference to request_distributor.sv attached in report) As the solvers solve pixels of the output tile, they write the results to SDRAM. Arbitration logic collects results from any solvers which are ready to write. (I assume this is with reference to write_arbitrator.sv attached in report)" Additional info: To my understanding, a top module (not attached to the report) is probably instantiating a multi_tile_solver.sv module and a module from Platform Designer, nothing more. As can be seen in the files in the report, multi_tile_solver.sv instantiates a request_distributor.sv module, a write_arbitrator.sv module, and NUM_SOLVERS tile_solver_legit.sv modules. Each tile_solver_legit.sv instantiates a solver.v, which instantiates a solver_control.v and a solver_datapath.v. It uses on-chip SRAM in the form of M10K block, which are created from the verilog source code, rather than having anything to do with the Platform Designer layout. I think I’m pretty close to running this amazing project, yet have been stuck on this platform designer layout and don’t succeed in finalizing. Any help would be much appreciated.DE1-SoC project compiles, but board programming fails 42%. Other programs work fine
Hello, After successfull Quartus compilation for a relatively simple project, programming the DE1-SoC fails when reaching 42%, with the following error: Info (209017): Device 2 contains JTAG ID code 0x02D120DD Error (209040): Can't access JTAG chain Error (209015): Can't configure device. Expected JTAG ID code 0x02D120DD for device 2, but found JTAG ID code 0x00000000. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf). I manage to program it with other designs, using the same .qsf file for the DE1-SoC from Cornell's ECE5760 site. Please see additional information in (Qsys layout, some Verilog I found relevant) at: https://electronics.stackexchange.com/questions/764588/de1-soc-project-compiles-but-board-programming-fails-42-other-programs-work-f It's much more comfortable to read it there. I've been trying to solve this issue for a very long time, any help will be much appreciated !
