Educational Hardware Request
Dear Altera University Program Team, My name is William Kleitz. I am a retired educator and the author of several digital electronics and FPGA textbooks published by Pearson Education. My 9th Edition textbook, which focuses heavily on Altera hardware and the Quartus software environment, has long been used in engineering programs and can be found on Amazon. I am currently coming out of retirement to develop a brand-new series of high-quality YouTube video tutorials and educational resources. My goal is to introduce the next generation of students and makers to modern digital design using the latest versions of Quartus Prime Lite. However, I have hit a hardware roadblock. The only development platforms I currently own are the original DE0 and DE0 Nano boards. Because these boards rely on the legacy Cyclone II chip, they are no longer supported by modern versions of Quartus, preventing me from recording up-to-date, relevant software workflows. To create this new curriculum, I would like to feature a modern, student-friendly platform. I am writing to ask if your university program would be open to donating a newer DE10-Lite development board (featuring the MAX 10 FPGA) to support this educational initiative. In return, your hardware will be the primary platform featured throughout my upcoming video series, exposing thousands of self-taught developers and students directly to your ecosystem. Thank you very much for your time, consideration, and continued support of engineering education. Warm regards, William (Bill) KleitzEducational DE 10 Hardware Request
My name is William Kleitz. I am a retired educator and the author of several digital electronics and FPGA textbooks published by Pearson Education. My 9th Edition textbook, which focuses heavily on Altera hardware and the Quartus software environment, has long been used in engineering programs and can be found on Amazon at - Kleitz- Digital Electronics Textbook. My YouTube videos can be found by searching Bill Kleitz VHDL I am currently coming out of retirement to develop a brand-new series of high-quality YouTube video tutorials and educational resources. My goal is to introduce the next generation of students and makers to modern digital design using the latest versions of Quartus Prime Lite. However, I have hit a hardware roadblock. The only development platforms I currently own are the original DE0 and DE0 Nano boards. Because these boards rely on the legacy Cyclone II chip, they are no longer supported by modern versions of Quartus, preventing me from recording up-to-date, relevant software workflows. To create this new curriculum, I would like to feature a modern, student-friendly platform. I am writing to ask if your university or academic relations program would be open to donating a newer DE10-Lite development board (featuring the MAX 10 FPGA) to support this educational initiative. In return, your hardware will be the primary platform featured throughout my upcoming video series, exposing thousands of self-taught developers and students directly to your ecosystem. Thank you very much for your time, consideration, and continued support of engineering education. Warm regards, William (Bill) Kleitz Textbook Author & Professor
DK-DEV-AGI027RES Install Package
I'd like to download an old outdated install package. It is for DK-DEV-AGI027RES. The link was removed a while back. Can someone at Altera please find the install package for me? A .qsf file with all the pinouts (e.g. golden_top.qsf in the install package) defined would work too.
AXC3000 Agilex 3 board
Hi, for a new design I'm starting to use an evaluation board from Arrow Electronics, (but designed by trenz electronics) with Agilex 3 https://github.com/ArrowElectronics/Agilex-3/wiki/Agilex-3-AXC3000-Development-Platform This board has an Hyperam W957D8NBRA4I installed but the Nios V example design uses only internal RAM. Anyone knows if the IP to use this ram is free into quartus or is necessary to acquire a license? Thanks
Agilex 5 reconfigurable PLL - emif
Trying to reconfig a PLL with the EMIF Calibration IP debug via system console Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs enabled dynamic config within IOPLL and included EMIT Calib. writing to divide setting addresses -> changes are immediate multiple pure phase shifts did not work (work randomly) is there a bit to start the shift with one design setting N - M - C worked but no multiple shifts with an other design problems writing to 0x80 to reset pll after setting NMC, no replay for new nmc setting 6.4.1 enable | 6.4.2 clear calib | 6.4.3 reconfig | 6.4.4 recal for just phase shifting 6.4.1 read modify write 6.4.3 without 0x80 2.2.12 perform positive or negative phase shift - is there a bit for that? Where did I go wrong?
Regarding data for the Altera Arria V GX FPGA development kit
I am looking for information on an Altera Arria V evaluation board that is equipped with the SFP module. I think that Arria V GX FPGA Development Kit is the relevant product. However, when I check the links below, I see “Error 404: Page Not Found.” Are the following links incorrect? Arria V GX FPGA Development Board Reference Manual (English, PDF) http://www.altera.com/literature/manual/rm_avgx_fpga_dev_board.pdf Arria V GX FPGA Development Kit User Guide (English, PDF) http://www.altera.com/literature/ug/ug_avgx_fpga_dev_kit.pdf Kit installer ftp://ftp.altera.com/outgoing/devkit/12.0/arriaVGX_5agxfb3hf40es_fpga_v12.0.0.exe Please provide the correct links. Best regards, Hachiware.
