DE10-Lite and sdram controller ip
Hello i have de10-lite and in the past i used sdram-controller ip in platform designer to connect the onboard ram to the nios processor. Now (25.1) it seems that this sdram controller is no more supported and I find nothing to replace it. The ddram controllers seems to be more complicated and I can’t figure out how to use their in this case. Someone coud help me ? Thanks
Does the FPGA N3000 support OpenCL and OneApi?
I received an INTEL FPGA PAC N3000 card, and taking the opportunity, I decided to learn how to develop with SYCL and oneAPI. However, I ran into problems. I fully installed the FPGA PAC N3000 Acceleration Stacks v1.3.1 and also updated the board's BMC from D.1.0.12 to D.2.0.19. Then I started configuring oneAPI 2022 using intel-basekit and fpga-addon, but proper configuration requires bsp, and I couldn't find it anywhere. I also saw that on the website page for Quartus Prime Pro 19.2, which is installed with IAS 1.3.1, there's a tab with oneAPI and BSPs for boards. I looked at other versions, but I only found mentions of Arria 10-GX and Arria 10-SX. I'm not sure if this will help, but the log is from CentOS 7.6.1810. [root@node-fpga ~]# fpgainfo fme Board Management Controller, MAX10 NIOS FW version D.2.0.19 Board Management Controller, MAX10 Build version D.2.0.6 //****** FME ******// Object Id : 0xF300000 PCIe s:b:d.f : 0000:84:00.0 Device Id : 0x0b30 Numa Node : 1 Ports Num : 01 Bitstream Id : 0x23000110010309 Bitstream Version : 0.2.3 Pr Interface Id : f3c99413-5081-4aad-bced-07eb84a6d0bb Boot Page : user [root@node-fpga ~]# fpgainfo bmc Board Management Controller, MAX10 NIOS FW version D.2.0.19 Board Management Controller, MAX10 Build version D.2.0.6 //****** BMC SENSORS ******// Object Id : 0xF300000 PCIe s:b:d.f : 0000:84:00.0 Device Id : 0x0b30 Numa Node : 1 Ports Num : 01 Bitstream Id : 0x23000110010309 Bitstream Version : 0.2.3 Pr Interface Id : f3c99413-5081-4aad-bced-07eb84a6d0bb ( 1) Board Power : 59.65 Watts ( 2) 12V Backplane Current : 2.91 Amps ( 3) 12V Backplane Voltage : 11.92 Volts ( 4) 1.2V Voltage : 1.20 Volts ( 6) 1.8V Voltage : 1.80 Volts ( 8) 3.3V Voltage : 3.27 Volts (10) FPGA Core Voltage : 0.90 Volts (11) FPGA Core Current : 14.47 Amps (12) FPGA Core Temperature : 62.50 Celsius (13) Board Temperature : 42.00 Celsius (14) QSFP A Voltage : N/A (15) QSFP A Temperature : N/A (24) 12V AUX Current : 2.08 Amps (25) 12V AUX Voltage : 11.97 Volts (37) QSFP B Voltage : N/A (38) QSFP B Temperature : N/A (44) Retimer A Core Temperature : 63.00 Celsius (45) Retimer A Serdes Temperature : 64.00 Celsius (46) Retimer B Core Temperature : 0.00 Celsius (47) Retimer B Serdes Temperature : 0.00 Celsius [root@node-fpga ~]# aoc -list-boards Board list: pac_a10 (default) Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac pac_s10 Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_s10sx_pac pac_s10_usm Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_s10sx_pac Memories: device, host [root@node-fpga ~]# aocl list-devices -------------------------------------------------------------------- Device Name: acl0 BSP Install Location: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac Vendor: Intel Corp Physical Dev Name Status Information pac_f200000 Uninitialized OpenCL BSP not loaded. Must load BSP using command: 'aocl program <device_name> <aocx_file>' before running OpenCL programs using this device DIAGNOSTIC_PASSED -------------------------------------------------------------------- [root@node-fpga ~]# aocl initialize acl0 pac_a10 aocl initialize: Running initialize from /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac/linux64/libexec bitstream.c:391:validate_bitstream_metadata() **ERROR** : Interface ID check failed Error writing bitstream to FPGA: invalid parameter Error programming device aocl initialize: Program failed. [root@node-fpga ~]#
About old Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board...
I can see that the old version of Quartus has come back, so I will give it a chance. Could Altera offical upload the "SIIGX_SI_Kit-v1.0.1.exe" file again for "Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board"? Any help would be appreciated.
EPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!
Process for RMA - Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Hello there, I have an Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (https://www.altera.com/products/devkit/a1jui0000049utomam/agilex-7-fpga-i-series-transceiver-development-kit-6x-f-tile) that has recently stopped functioning correctly. In particular, the JTAG chain does recognize the existence of the Agilex FPGA. Quartus's JTAG debugger throws an error: Error: TDI connection to the first detected device 10M16S(A|C|L) might be shorted to GND Error: The TCK and TMS connections to the device before the first detected device 10M16S(A|C|L) might have a problem Info: Detected 1 device(s) Info: Device 1: 10M16S(A|C|L) When trying different settings on the JTAG chain selection mux, it is clear that the System MAX10 is detected and functioning correctly, but the Agilex FPGA cannot be detected. We have tried to reprogram the MAX10 with the factory default image, but there has been no change. We suspect a hardware issue with the JTAG chain. At this point, the Agilex FPGA is not accesible, rendering the board unusable for our purpose. Could ALTERA please support us on this? Is it possible to start the process for an RMA? Are there any options that we can consider? We greatly appreciate your assistance in this time of need Thank you
JTAG Chain Broken – Unable to Program Agilex 5 Modular Development Board
Hi, I recently started working with the Agilex 5 Modular Development Board, and it suddenly can no longer be programmed. The USB cable in use is known to be working. When I connect the cable, it is detected, but when I run the “Auto Detect” option in the Quartus Programmer, I receive the following message: When running the JTAG Chain Test, I see the following result: I also tried using the Configuration Debugger, but when I attempt to select the hardware cable, I encounter Error code 87: I would appreciate any help in resolving this issue, and I can provide additional details or logs if needed.DK-DEV-AGI027RES Install Package
I'd like to download an old outdated install package. It is for DK-DEV-AGI027RES. The link was removed a while back. Can someone at Altera please find the install package for me? A .qsf file with all the pinouts (e.g. golden_top.qsf in the install package) defined would work too.
