DK-DEV-AGI027RES Install Package
I'd like to download an old outdated install package. It is for DK-DEV-AGI027RES. The link was removed a while back. Can someone at Altera please find the install package for me? A .qsf file with all the pinouts (e.g. golden_top.qsf in the install package) defined would work too.
Agilex 5 reconfigurable PLL - emif
Trying to reconfig a PLL with the EMIF Calibration IP debug via system console Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs enabled dynamic config within IOPLL and included EMIT Calib. writing to divide setting addresses -> changes are immediate multiple pure phase shifts did not work (work randomly) is there a bit to start the shift with one design setting N - M - C worked but no multiple shifts with an other design problems writing to 0x80 to reset pll after setting NMC, no replay for new nmc setting 6.4.1 enable | 6.4.2 clear calib | 6.4.3 reconfig | 6.4.4 recal for just phase shifting 6.4.1 read modify write 6.4.3 without 0x80 2.2.12 perform positive or negative phase shift - is there a bit for that? Where did I go wrong?
Regarding data for the Altera Arria V GX FPGA development kit
I am looking for information on an Altera Arria V evaluation board that is equipped with the SFP module. I think that Arria V GX FPGA Development Kit is the relevant product. However, when I check the links below, I see “Error 404: Page Not Found.” Are the following links incorrect? Arria V GX FPGA Development Board Reference Manual (English, PDF) http://www.altera.com/literature/manual/rm_avgx_fpga_dev_board.pdf Arria V GX FPGA Development Kit User Guide (English, PDF) http://www.altera.com/literature/ug/ug_avgx_fpga_dev_kit.pdf Kit installer ftp://ftp.altera.com/outgoing/devkit/12.0/arriaVGX_5agxfb3hf40es_fpga_v12.0.0.exe Please provide the correct links. Best regards, Hachiware.
AXC3000 Agilex 3 board
Hi, for a new design I'm starting to use an evaluation board from Arrow Electronics, (but designed by trenz electronics) with Agilex 3 https://github.com/ArrowElectronics/Agilex-3/wiki/Agilex-3-AXC3000-Development-Platform This board has an Hyperam W957D8NBRA4I installed but the Nios V example design uses only internal RAM. Anyone knows if the IP to use this ram is free into quartus or is necessary to acquire a license? Thanks
LLM Implementation on Agilex 5 E-Series 065B Modular Dev Kit
I am currently working on deploying Large Language Model (LLM) inference using FPGA AI Suite on the Agilex 5 E-Series 065B Modular Development Kit. I have two clear and specific questions: Is the Agilex 5 E-Series 065B officially supported for LLM / Transformer inference with FPGA AI Suite? Is the following workflow officially supported for LLM inference on this board? Step 1: Export a pre-trained LLM from Hugging Face to OpenVINO IR format using optimum-intel Step 2: Generate the target FPGA architecture file using architecture_optimizer for Agilex 5. Step 3: Compile the OpenVINO IR model for the FPGA using: • dla_compiler → for Sequential flow, or • Spatial Compiler → for Spatial flow. Step 4: Integrate the generated FPGA AI Suite IP into a Quartus Prime project, generate the bitstream, and program it onto the Agilex 5 E-Series 065B board. Step 5: Run inference using the FPGA AI Suite runtime (host application). I understand this may not be a push-button process and could require significant modifications to the generated RTL — but is this workflow still considered a viable starting point for implementing LLM / Transformer inference on the Agilex 5 E-Series 065B? Thank you.Fitter error in A5ED043AB23AI2V Example design
Hi, I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V. During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually. Could you please help me understand how to resolve this issue?
Verifying R-Tile PIPE Direct x8 lane-to-pin mapping on Agilex 7 I-Series Dev Kit
Hi all, I am bringing up a custom PCIe Gen5 controller on the Intel Agilex 7 I-Series Development Kit using the R-Tile Hard IP in PIPE Direct mode (1×16 bundle, only Octet 0 / lanes 0–7 active for now). The soft logic above PIPE (LTSSM, TX TS1/TS2 generation, RX word aligner, 8b/10b decode) is custom RTL. Symptom During Polling.Active, only 2 of 8 lanes ever reach wa_locked = 1 in my soft K28.5-comma word aligner. The other 6 lanes stay in SEARCH/VERIFY indefinitely. The 2 locking lanes are not always the same pair across resets, which makes me suspect either (a) a per-lane CDR / rx_valid gating issue, or (b) a lane-to-pin mapping mismatch between my QSF and the actual PCIe edge connector routing on the dev kit. Before I dig deeper into the CDR / rxdatavalid side, I would like to sanity-check the pin assignments below against the official Agilex 7 I-Series Dev Kit schematic / pin-out, because if lanes are physically swapped vs. what the host RC expects, only the lanes that happen to land on lane 0 (and possibly its mirror) would ever see TS1 ordered sets. Pin assignments in pipe_direct.qsf (Octet 0, lanes 0–7) Signal Pin Signal Pin refclk0 DR68 refclk1 CU68 pin_perst_n CD58 tx_p_out0 / tx_n_out0 DL74 / DH73 rx_p_in0 / rx_n_in0 DE82 / DB83 tx_p_out1 / tx_n_out1 DB77 / DE76 rx_p_in1 / rx_n_in1 CW80 / CT79 tx_p_out2 / tx_n_out2 CW74 / CT73 rx_p_in2 / rx_n_in2 CM82 / CJ83 tx_p_out3 / tx_n_out3 CJ77 / CM76 rx_p_in3 / rx_n_in3 CF80 / CC79 tx_p_out4 / tx_n_out4 CF74 / CC73 rx_p_in4 / rx_n_in4 BY82 / BU83 tx_p_out5 / tx_n_out5 BU77 / BY76 rx_p_in5 / rx_n_in5 BP80 / BL79 tx_p_out6 / tx_n_out6 BP74 / BL73 rx_p_in6 / rx_n_in6 BH82 / BE83 tx_p_out7 / tx_n_out7 BE77 / BH76 rx_p_in7 / rx_n_in7 BB80 / AW79 IO standards: HCSL for refclk0/1, HIGH SPEED DIFFERENTIAL I/O for all TX/RX, 1.0V for pin_perst_n. Lanes 8–15 (Octet 1) are assigned in the QSF as well but are intentionally excluded from the active datapath in this build. Specific questions Are the lane 0–7 TX/RX pin numbers above the correct mapping for the PCIe edge connector on the Agilex 7 I-Series Dev Kit when the R-Tile is configured as a PIPE Direct 1×16 bundle and only the lower octet is used as a x8 link? For PIPE Direct 1×16 with Octet 0 active, is refclk0 (PIN_DR68) the correct refclk source, or does the bundle require both refclk0 and refclk1 driven from the same 100 MHz source even though only 8 lanes are used? Are there any lane-reversal / polarity-inversion considerations on this dev kit that I would need to handle in soft logic vs. inside the R-Tile IP (i.e. does the IP already account for board-level lane reversal so that lane 0 in RTL is guaranteed to be lane 0 at the connector)? Any pointer to the authoritative pin-out table for this board's PCIe edge connector would be very helpful. Thanks!AGILEX 5 cvp mode
Hello, I'm using the Arrow Eagle board and trying to use CVP mode. I've flashed the JIC file and am now trying to upload the core.rbf file using this command echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name but the directory /sys/kernel/debug/fpga_manager/ does not exist. I noticed that the directory /sys/class/fpga_manager/fpga0/ exists, but there is no firmware_name file ls /sys/class/fpga_manager/fpga0/ => device/ name power/ state status subsystem/ uevent How can I resolve this issue?
