Device stopped receiving config data: Internal error (0x0000, 0x00000000, 0x1800).
Using Agilex AGFB014R24A (E-Tile board). .jic flashes successfully, but no UART logs are observed after boot. Observed attached logs attached When programming the corresponding .sof via JTAG, configuration fails at ~86%. Device has stopped receiving configuration data Error message received from device: Internal error. (Subcode 0x0000, Info 0x00000000, Location 0x00001800) Operation failed Ended Programmer operation Looking for clarification on this internal error and recommended workaround.
Stratix 10 GX SI Board - issue with the Board Test System (BTS)
We recently purchased several Stratix 10 GX Signal Integrity development boards and would appreciate your advice regarding an issue with the Board Test System (BTS). When attempting to program the FPGA using the .sof files available under the Configure tab in BTS, none of the designs can be successfully programmed. The system consistently reports: “Detected bts_config.sof on FPGA.” It appears that the FPGA remains running the default bts_config.sof, and the selected configurations do not load as expected. This happens when the Quartus version in the QUARTUS_ROOTDIR is the Quartus standard. If I change it to Quartus Pro version ( I tried 22.1 24.1 and 25.1), the BTS will not be open, and it gets stuck at "Setup connection to System Console server". Could you please let us know whether this is a known issue and advise on how to resolve it? I think it might be related to the version of Quartus we use. If so, please can you suggest which latest version we should use for the BTS? Thank you very much for your assistance. Best regards, Toni771
About PCIe Daughter Cards for Agilex™ 3 FPGA and SoC C‑Series Development Kit
Dear Support Team, I would like to ask for clarification regarding the PCIe add‑in cards for the Agilex™ 3 FPGA and SoC C‑Series Development Kit. In the User Guide, Table 5. Available PCIe Daughter Cards lists the following two models: 3.3. Modes of Operations • Agilex™ 3 FPGA and SoC C-Series Development Kit User Guide • Altera Documentation and Resources Center ・DC-A3PCIE ・DC-A3SOCPCIE Could you please provide documentation that explains the differences between these two daughter cards—such as their appearance, functionality, or any other technical distinctions? I have already downloaded the installer package for the development kit, but the documents folder was empty, and I could not find detailed information about these PCIe daughter cards. If there is a specific document, datasheet, or application note that describes these two cards in more detail, I would appreciate it if you could point me to the correct resource. Thank you very much for your support. Best regards, Gesso
Available replacement for the discontinued P/N: MK-A5E065BB32AES1 ?
Hello, PDN: https://www.mouser.com/PCN/Intel_Corporation_PDN2513.pdf?srsltid=AfmBOoqEg4CcKdQVpDMH8g2nQDlihxYoQoJwu3Bcg91PBuKx__G1W-Mf is suggesting P/N: MK-A5E065BB32AEA (Future) as replacement for the already discontinued P/N: MK-A5E065BB32AES1 A customer is desperately searching for this old or the new board, or an alternative that would be immediately available for an important project. His previous order was not considered any more, unfortunately. Can you possibly help to get hold of one of these boards, or would you know a reseller who might still have stock? Thank you very much Best regards Adnan (ref: Q1CDFE8)
Quartus Assembler License Error: Unlicensed IP 56CC 2480 & 2493 in Bitec HDMI 2.1 eARC Demo
Hi, I am currently working with the Bitec FMC HDMI 2.1 Daughter Card (Rev9) on an Arria 10 FPGA (using Quartus Prime 20.4). I am encountering a licensing issue when running the provided eARC demo (bitec_hdmi/earc). The Problem: The Assembler fails to generate the .sof file with the following error messages: Steps Taken: License Setup: I have already added the following Bitec license files to the Quartus License Setup. The licenses appear to be active in the License Setup window, but the "Unknown 56CC" error persists during the assembly stage. Quartus Version: I am using Quartus Prime Pro 20.4. Questions: 1. Is there any way to run and generate the programming files for this Bitec HDMI eARC demo? 2. Is there a known compatibility issue between these IP cores and Quartus 20.4? 3. Are there any additional environment variables or settings I should check to ensure these encrypted files are properly recognized? Any guidance or suggestions would be greatly appreciated. Thank you!
Differential Signal Transmitter on Agilex 5 FPGA Modular Dev Kit
We will use the SOM Module of the Agilex 5 FPGA E-Series 065B Modular Development Kit (MK-A5E065BB32AES1) for a new project with our own designed carrier board. For this design we need multiple differential transmit and receive signals from I/O Bank 2A_B and 2A_T (→ 1.2V bank supply). We started with a basic design to evaluate usable I/O Standards. We have seen that we can use differential receiver with the 1.2V bank supply but it is not possible to use "True Differential Signaling" on transmit pins with 1.2V bank supply. For our purpose it is necessary to generate differential transmit signals correctly working with LVDS inputs on the receiver site. Is there an alternative differential signal output generating a correct LVDS signal for a LVDS receiver working with the 1.2V bank supply (e.g. POD12 with special termination)? What happens when setting differential transmit and receive pins to "1.3V True Differential Signaling" to get Quartus running without an error but physically using only 1.2V bank supply? Will this only decrease signal swing on transmit pins or is this not working? Or could this damage the FPGA transmit and receive pins of the FPGA? The SOM schematic does not show any possibility to disconnect the I/O Banks 2A_B and 2A_T from onboard 1.2V supply to use an alternative external 1.3V supply. Is there the a possibility to supply these banks externally by 1.3V? Which other alternatives do we have to get differential signaling output working?DK-SI-AGI040FES KIT: Agilex™ 7 F-Series and I-Series ES Device Errata
Hello ! Please help us to get this errata document. We got Agilex-7 I-Series Kit ES1 6xF-Tile (DK-SI-AGI040FES) with AGIC040R39A2E2VR0 device and need errata document for ES1 device to departure from kit package sample designs with clear understanding ES1 device limitation while building own designs for the device in the kit. All applications through Intel access gets all time denials without any explanations, links and even FAE contact information. Wasted $15K on this kit and cannot get any support, terrible experience with Intel. This ES errata document is mentioned in Agilex™ 7 F-Series and I-Series Known Issue List. https://docs.altera.com/r/docs/683584/current/agilextm-7-f-series-and-i-series-known-issue-list/about-this-document Here is screenshot Its also still available in old I-series datasheets that are hosted on Mouser and Digikey: https://www.mouser.com/pdfDocs/ug-agilex-i-fpga-devl-kit-683288-6772523.pdf Here is screen shot: This is link to get datasheet but I cannot get permission to it: https://cdrdv2.intel.com/v1/dl/getContent/612877?explicitVersion=true !!! AND PLEASE DO NOT DELETE MY QUESTIONS !!!! Best regards, Sam
