Why 390.625MHz clock to F-Tile Reference fequency

Hi,

This question is regarding the Agilex 7 M-Series FPGA Development Kit.

In the evaluation board schematics, the Si5518 provides a 390.625 MHz clock that is connected to two F-Tile reference clock inputs.

From the F-Tile Ethernet Hard IP User Guide, I understand that standard Ethernet designs typically use 156.25 MHz as the PMA reference clock, while the 390.625 MHz clock appears internally as the clk_txmac/clk_rxmac clock.

My questions are:

1. Which F-Tile configuration or interface is intended to use the external 390.625 MHz reference clock on the development board?

2. Is this reference intended for the Ethernet Hard IP, PMA Direct mode, SyncE, or some other transceiver application?

3. Are there any official reference designs that use this 390.625 MHz reference clock?

I would appreciate it if you could clarify the intended use of this clock on the Agilex M Development Kit.

Regards,