Hi Team, We recently purchased license for the ARM DS5 IDE from Altera with License file contains note as NOTICE="For use with Intel or Altera devices only". I am using Arm Development studio IDE with version 2025.1-1. ALtera Agilex 5 FPGA device configured with custom soft macro based design which is only having ARM Cortex M55 processor cores with coresight debug IP . My question is whether ARM DS IDE will detect, access and debug the Cortex M55 cores which is in the fpga through the JTAG USB Blaster ? Please provide the detailed explanation RegardsSuresh

Hi Suresh430 For debugging the Agilex5 FPGA Devices, you could use the Ashling IDE which is Free to download. Below are some useful links to have a look: https://www.altera.com/products/development-tools/ashling https://altera-fpga.github.io/rel-25.3.1/demos/agilex-5/e-series/premium/riscfree-debug-linux/ug-riscfree-debug-linux-agx5e-premium/

Hi Suresh430 Please let me know if you require any further clarification regarding this case.

Hi Team,We are working on Agilex 5 (Sulfur evaluation board) with a custom FPGA design that integrates:ARM Cortex-M55 soft macroCoreSight Debug Access Port (DAP)Debug logic connected internallyCurrent connection flow is:Debugger (Host PC) → Altera USB Blaster → Virtual JTAG → CoreSight DAP → Cortex-M55Key Clarifications Required : Virtual JTAG vs Native JTAG AccessCurrently, the CoreSight DAP JTAG signals are routed through Virtual JTAG inside the FPGA fabric.Is this architecture supported for external debuggers (ARM DS / Ashling)?Can CoreSight DAP be reliably accessed via Virtual JTAG, or is this approach not recommended? JTAG Requirement : Do we need two separate JTAG interfaces?One for FPGA configuration (via USB Blaster)Another dedicated ARM debug JTAG (DAP access)Debugger Tool Compatibility : Will ARM Development Studio (DS-5 / ADS) be able to:Detect Cortex-M55 through this setup?Access CoreSight components via Virtual JTAG? Or is Ashling RiscFree IDE + probe mandatory for this configuration?Debugger Hardware Recommendation : In case Virtual JTAG is not sufficient:Which debug probe/cable is recommended for Cortex-M55 debug?ULINK?DAPLink?Ashling probe?Can USB Blaster be used for CoreSight debugging, or is it limited to FPGA configuration/debug only?a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; }Reference Design / Best Practice :Could you please share:Any reference design or documentation showing proper integration of:Cortex-M55 soft coreCoreSight DAPJTAG/debug interface in Agilex 5 FPGARegardsSuresh

Hi Suresh430 Yes the ARM DS could be used to detect the Cortex-M55 through the jtag chain as long the ARM DS-5 supports the CoreSight SOC-600. The Virtual JTAG IP could not be used to debug Cortex-M55, the connection will need to go through the native Jtag connection. From my understanding of the Virtual Jtag IP, this IP is used as a connection for IPs in the fabric to be connected to the jtag chain.

Hi Tehjingy,Thank you for the clarification that Virtual JTAG cannot be used for Cortex‑M55 debug and that native JTAG access is required.To proceed further, we would like to clarify a few implementation details:1. Native JTAG IntegrationIn Agilex 5 FPGA, the external JTAG interface is already occupied by the Intel Hard TAP for configuration/debug.👉 How can we connect the CoreSight DAP (JTAG-DP) to the native JTAG pins?Is it possible to:Integrate the CoreSight DAP into the existing JTAG scan chain of the FPGA?Or is there a mechanism to bypass / extend the Intel TAP to expose the CoreSight DAP directly?2.Multiple JTAG InterfacesDo we need to provide:One JTAG for FPGA configuration (USB Blaster)A separate dedicated JTAG interface for ARM debug (DAP access)If yes:Are there any reference designs or guidelines for implementing dual JTAG interfaces on Agilex 5?3. Debug Probe CompatibilitySince USB Blaster is not suitable for CoreSight debugging:Which probe is officially recommended for Cortex‑M55 debug in FPGA-based systems?ULINK / DAPLink / DSTREAM / Ashling?Are there any constraints on:Supported probe types with ARM DS / ADS?JTAG vs SWD usage for this setup?4.CoreSight DAP Connection RequirementsTo ensure tool detection:Does the CoreSight DAP (JTAG-DP) need to be:Directly exposed on the JTAG scan chain (visible at top level)?Or can it be accessed via an intermediate routing logic (if compliant)?Are there specific requirements for:TAP ordering in scan chain?IDCODE / IR length alignment?5. Recommended ArchitectureCould you please confirm the correct/debuggable architecture for Agilex 5 + Cortex‑M55 soft core?Option A (preferred?): External Debug Probe → Native JTAG → CoreSight DAP → Cortex‑M55Option B (current – not working): USB Blaster → Intel TAP → Virtual JTAG → DAP → Cortex‑M55RegardsSuresh

ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device

13 Replies

tehjingy_Altera
Regular Contributor
2 months ago
Hi Suresh430

For debugging the Agilex5 FPGA Devices, you could use the Ashling IDE which is Free to download.

Below are some useful links to have a look:

https://www.altera.com/products/development-tools/ashling

https://altera-fpga.github.io/rel-25.3.1/demos/agilex-5/e-series/premium/riscfree-debug-linux/ug-riscfree-debug-linux-agx5e-premium/
tehjingy_Altera
Regular Contributor
1 month ago
Hi Suresh430

Please let me know if you require any further clarification regarding this case.
- Suresh430
  New Contributor
  1 month ago
  Hi Team,
  We are working on Agilex 5 (Sulfur evaluation board) with a custom FPGA design that integrates:
  ARM Cortex-M55 soft macro
  CoreSight Debug Access Port (DAP)
  Debug logic connected internally
  Current connection flow is:
  Debugger (Host PC) → Altera USB Blaster → Virtual JTAG → CoreSight DAP → Cortex-M55
  Key Clarifications Required :
  Virtual JTAG vs Native JTAG Access
  Currently, the CoreSight DAP JTAG signals are routed through Virtual JTAG inside the FPGA fabric.
  Is this architecture supported for external debuggers (ARM DS / Ashling)?
  Can CoreSight DAP be reliably accessed via Virtual JTAG, or is this approach not recommended?
  JTAG Requirement :
  Do we need two separate JTAG interfaces?
  One for FPGA configuration (via USB Blaster)
  Another dedicated ARM debug JTAG (DAP access)
  Debugger Tool Compatibility :
  Will ARM Development Studio (DS-5 / ADS) be able to:Detect Cortex-M55 through this setup?Access CoreSight components via Virtual JTAG? Or is Ashling RiscFree IDE + probe mandatory for this configuration?
  Debugger Hardware Recommendation :
  In case Virtual JTAG is not sufficient:
  Which debug probe/cable is recommended for Cortex-M55 debug?
  ULINK?
  DAPLink?
  Ashling probe?
  Can USB Blaster be used for CoreSight debugging, or is it limited to FPGA configuration/debug only?
  a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; }
  Reference Design / Best Practice :
  Could you please share:
  Any reference design or documentation showing proper integration of:
  Cortex-M55 soft core
  CoreSight DAP
  JTAG/debug interface in Agilex 5 FPGA
  
  Regards
  Suresh
  - tehjingy_Altera
    Regular Contributor
    1 month ago
    Hi Suresh430
    
    Yes the ARM DS could be used to detect the Cortex-M55 through the jtag chain as long the ARM DS-5 supports the CoreSight SOC-600.
    
    The Virtual JTAG IP could not be used to debug Cortex-M55, the connection will need to go through the native Jtag connection.
    
    From my understanding of the Virtual Jtag IP, this IP is used as a connection for IPs in the fabric to be connected to the jtag chain.

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ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device

13 Replies

Key Clarifications Required :

JTAG Requirement :

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