Forum Discussion
New ContributorARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
New ContributorHi Team,
We are working on Agilex 5 (Sulfur evaluation board) with a custom FPGA design that integrates:
- ARM Cortex-M55 soft macro
- CoreSight Debug Access Port (DAP)
- Debug logic connected internally
- Current connection flow is:
Debugger (Host PC) → Altera USB Blaster → Virtual JTAG → CoreSight DAP → Cortex-M55
Key Clarifications Required :
- Virtual JTAG vs Native JTAG Access
- Currently, the CoreSight DAP JTAG signals are routed through Virtual JTAG inside the FPGA fabric.
- Is this architecture supported for external debuggers (ARM DS / Ashling)?
- Can CoreSight DAP be reliably accessed via Virtual JTAG, or is this approach not recommended?
- Virtual JTAG vs Native JTAG Access
JTAG Requirement :
- Do we need two separate JTAG interfaces?
- One for FPGA configuration (via USB Blaster)
- Another dedicated ARM debug JTAG (DAP access)
Debugger Tool Compatibility :
Will ARM Development Studio (DS-5 / ADS) be able to:Detect Cortex-M55 through this setup?Access CoreSight components via Virtual JTAG? Or is Ashling RiscFree IDE + probe mandatory for this configuration?
Debugger Hardware Recommendation :
- In case Virtual JTAG is not sufficient:
- Which debug probe/cable is recommended for Cortex-M55 debug?
- ULINK?
- DAPLink?
- Ashling probe?
- Which debug probe/cable is recommended for Cortex-M55 debug?
- Can USB Blaster be used for CoreSight debugging, or is it limited to FPGA configuration/debug only?
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Reference Design / Best Practice :
- Could you please share:
- Any reference design or documentation showing proper integration of:
- Cortex-M55 soft core
- CoreSight DAP
- JTAG/debug interface in Agilex 5 FPGA
- Any reference design or documentation showing proper integration of:
Regards
Suresh
Regular ContributorHi Suresh430
Yes the ARM DS could be used to detect the Cortex-M55 through the jtag chain as long the ARM DS-5 supports the CoreSight SOC-600.
The Virtual JTAG IP could not be used to debug Cortex-M55, the connection will need to go through the native Jtag connection.
From my understanding of the Virtual Jtag IP, this IP is used as a connection for IPs in the fabric to be connected to the jtag chain.
- Suresh430
Hi Tehjingy,
Thank you for the clarification that Virtual JTAG cannot be used for Cortex‑M55 debug and that native JTAG access is required.
To proceed further, we would like to clarify a few implementation details:
1. Native JTAG Integration- In Agilex 5 FPGA, the external JTAG interface is already occupied by the Intel Hard TAP for configuration/debug.
- 👉 How can we connect the CoreSight DAP (JTAG-DP) to the native JTAG pins?
- Is it possible to:
- Integrate the CoreSight DAP into the existing JTAG scan chain of the FPGA?
- Or is there a mechanism to bypass / extend the Intel TAP to expose the CoreSight DAP directly?
2.Multiple JTAG Interfaces
- Do we need to provide:
- One JTAG for FPGA configuration (USB Blaster)
- A separate dedicated JTAG interface for ARM debug (DAP access)
- If yes:
- Are there any reference designs or guidelines for implementing dual JTAG interfaces on Agilex 5?
3. Debug Probe Compatibility
Since USB Blaster is not suitable for CoreSight debugging:
- Which probe is officially recommended for Cortex‑M55 debug in FPGA-based systems?
- ULINK / DAPLink / DSTREAM / Ashling?
- Are there any constraints on:
- Supported probe types with ARM DS / ADS?
- JTAG vs SWD usage for this setup?
4.CoreSight DAP Connection Requirements
To ensure tool detection:
- Does the CoreSight DAP (JTAG-DP) need to be:
- Directly exposed on the JTAG scan chain (visible at top level)?
- Or can it be accessed via an intermediate routing logic (if compliant)?
- Are there specific requirements for:
- TAP ordering in scan chain?
- IDCODE / IR length alignment?
5. Recommended Architecture
Could you please confirm the correct/debuggable architecture for Agilex 5 + Cortex‑M55 soft core?
Option A (preferred?): External Debug Probe → Native JTAG → CoreSight DAP → Cortex‑M55
Option B (current – not working): USB Blaster → Intel TAP → Virtual JTAG → DAP → Cortex‑M55
Regards
Suresh
- tehjingy_Altera
Hi Suresh430
By default the DAP is exposed in the native JTAG connection daisy chained to the SDM.
When the HPS is enabled in the design, the DAP will appear in the jtag scan.
If you would like a separate JTAG connection specifically for the DAP, you could enable the SWJ-DP JTAG interface under the HPS IP.
This would export a conduit which you could connect it to a separate JTAG connection.
Recommended architecture is to have Option A which is implementation in our Devkits.
Option A : External Debug Probe → Native JTAG → CoreSight DAP → Cortex‑M55
- Suresh430
Hi Tehjingy,
Thank you for the clarification.
A follow up question is
In a custom design containing only Cortex-M55 and CoreSight components (without using the standard HPS processing system), will the DAP still appear in the native JTAG scan chain, or is additional integration required?
Thank you again for your support and guidance.
Regards,
Suresh Kumar Bandi
