MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry H
Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue
The FMC VCC IO voltage level is adjustable using a resistor on the board as shown below. The default is 1.8V and that works fine. When I depopulate the resistor (R468) to get 1.2V, the output voltage goes to 0V and the enable line for the DC-DC converter also goes low. Any idea what the reason for this is? And what is the fix?
Technical Assistance Request for Stratix® 10 SX SoC Development Kit (so#488775)
Hello all, PN#DK-SOC-1SSX-H-D PO#029-CA574 QTY: 1 Our customer used above board and had below questions, could you help check and give us solutions? “Please help to confirm whether the FMC IO voltage on this development board supports 1.2 V. If it is supported, could you please advise how the FMC IO voltage can be configured to 1.2 V (for example, via hardware settings, jumpers, or power configuration)? Any relevant documentation or guidance would be greatly appreciated.” Thank you.
A question about reading the configuration space of the R-Tile PCIe IP EP
Hello, Recently, I generated an EP device using the R-Tile PCIe IP, and I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 as 0x002100B0, while the .xlsx file states it is 0x000800B0. Shouldn't the PCIe configuration space be 4KB? Why are 16-bit address lines being used to access the configuration space? Given that the read data width is 8 bits, does a value of a configuration register (32 bits) need to be read four times to be obtained? If I want to know the bus number and device number of the EP device in the user logic, can I directly obtain these from the configuration registers? Thank you! Recently, I generated an EP device using the R-Tile PCIe IP. I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 is 0x002100B0, while the .xlsx file states it is 0x000800B0. Additionally, shouldn’t the PCIe configuration space be 4KB? Why are 16-bit address lines used to access the configuration space? Furthermore, if I want to know the bus number and device number of the EP device in the user logic, can I directly obtain them from the configuration registers? Thank you!Failed to get MAX10 Triple Speed Ethernet example design to compile
Greetings Altera Experts, I have been trying to recreate an ALTER example design for a MAX 10 Development kit :: "MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide" The problem is that when i read in the max10tse_q_18_0_std.par into a new Quartus project using the same version of Quartus in which the project was originally created from (QUARTUS STD 18.0) it seems to go through initial enumerate and synthesis part OK but then when i try to open the QSYS Platform i see a load of RED errors due to missing components, which are these IP's: st_mux_2_to_1, aso_splitter, error_adapter2, eth_gen, eth_mon So basically most of the QSYS design apart from the TSE and a reset and clock are missing ! I tried to doing the 'upgrade IP' in Quartus for the Qsys component but that didn't help, and also i did a IP library refresh. Again no help. Does anybody got any suggestions please as to how to get these missing IP components ? Or is there a Git rep somewhere with a complete design i can compile for a MAX10 dev board using the Triple Speed Ethernet core ? I have attached the Altera User Guide for this example design to this case. I also added a screenshot showing the errors i get from loading up QSYS. Thanks for any help, Dr Barry H
nCONFIG and nSTATUS,CONF_DONE always LOW EP4CE6
Hello everyone, i has problem about hardware of EP4CE6E22C8, i configure initialize pin like under About power supply, i sure that every bank has right voltage. The problem is when i connected through USB Blaster, quartus cannot detect device, when measure initialize pin, i see voltage in nSTATUS, nCONFIG, CONF_DONE always 0V although 3v3 pull up work. I checked chip solder right, 3v3 work, nSTATUS, nCONFIG, CONF_DONE do not touch GND. What should i do next ? Thanks everyone.EPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!
Process for RMA - Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Hello there, I have an Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (https://www.altera.com/products/devkit/a1jui0000049utomam/agilex-7-fpga-i-series-transceiver-development-kit-6x-f-tile) that has recently stopped functioning correctly. In particular, the JTAG chain does recognize the existence of the Agilex FPGA. Quartus's JTAG debugger throws an error: Error: TDI connection to the first detected device 10M16S(A|C|L) might be shorted to GND Error: The TCK and TMS connections to the device before the first detected device 10M16S(A|C|L) might have a problem Info: Detected 1 device(s) Info: Device 1: 10M16S(A|C|L) When trying different settings on the JTAG chain selection mux, it is clear that the System MAX10 is detected and functioning correctly, but the Agilex FPGA cannot be detected. We have tried to reprogram the MAX10 with the factory default image, but there has been no change. We suspect a hardware issue with the JTAG chain. At this point, the Agilex FPGA is not accesible, rendering the board unusable for our purpose. Could ALTERA please support us on this? Is it possible to start the process for an RMA? Are there any options that we can consider? We greatly appreciate your assistance in this time of need Thank you
Agilex 3 AVST programming fails
Hi, We are trying to program an Agilex 3 device over the AVST8 interface, implemented through a CPU using SPI and bit-banging. Setup (see picture below): Data is shifted into a serial-to-parallel converter via SPI. AVST_CLK is generated from the SPI CS signal. AVST_VALID and AVST_READY are controlled by GPIOs. With this setup, we can mimic the passive serial programming approach used on Arria FPGAs. What works: Programming and testing over JTAG works fine. The FPGA design itself runs correctly. What does not work: During AVST8 programming, AVST_READY goes low after ~8210 bytes and never returns high. Programming sequence we follow: CPU initializes pins: nCONFIG=0, AVST_VALID=0 CPU sets nCONFIG=1 FPGA pulls nSTATUS=0 CPU sets nCONFIG=0 FPGA sets nSTATUS=1 CPU provides some clock cycles (~81 cycles) on AVST_CLK (since AVST_READY is low) FPGA sets AVST_READY=1 CPU sets AVST_VALID=1 and streams configuration data After 8210 cycles, FPGA sets AVST_READY=0 CPU sets AVST_VALID=0 and continues clocking At this point, AVST_READY never goes high again. What we observed: If we deliberately corrupt the configuration data, nSTATUS goes low after a few cycles — as expected. This suggests that the FPGA is checking data integrity, but something prevents AVST_READY from recovering. Our bit-banged AVST_CLK frequency is only about 60 kHz. Could this low frequency be the root cause? Question: Why does AVST_READY stay low after 8210 bytes? Is the slow clock (60 kHz) causing the issue, or are we missing something in the programming sequence? Thanks in advance for your support!
