Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs
Hello, I am developing a custom PCIe endpoint using the Agilex 7 R-Tile PIPE Direct interface. The PHY is provided by the R-Tile IP, while the LTSSM, Data Link Layer, and TLP/DLLP handling are implemented in soft RTL. Environment FPGA: Agilex 7 AGIB027R29A Quartus Prime Pro 24.3.0 Build 212 R-Tile PIPE Direct mode PCIe Gen3 x8 Custom soft LTSSM and Data Link Layer Linux host with a commercial PC/root complex The FPGA is configured before a host cold boot The endpoint is not currently visible in lspci In a successful Signal Tap capture: The LTSSM reaches Gen3 L0. The Data Link Layer reaches DL_ACTIVE. InitFC1 and InitFC2 for Posted, Non-Posted, and Completion traffic are exchanged. We observe valid incoming TLP traffic with a correct LCRC. The host sends a Message TLP that appears to decode as Set_Slot_Power_Limit. No subsequent Configuration Type 0 Read TLP or other expected enumeration TLP is observed. The link later returns from L0 to Recovery.RcvrLock. Our understanding is that Set_Slot_Power_Limit is a posted Message TLP and should not require a Completion TLP from the endpoint. The endpoint should only acknowledge successful reception at the Data Link Layer. Please correct us if this interpretation is wrong. Questions Is receiving Set_Slot_Power_Limit before the first Configuration Read a normal root-port enumeration sequence? Does the endpoint need to respond to this Message TLP in any way other than sending a Data Link Layer ACK? If the ACK DLLP has an incorrect sequence number, CRC, or timing, could the root port stop sending further TLPs and eventually force the link into Recovery? Are there any R-Tile PIPE Direct-specific status or control signals that must be handled before the host starts Configuration transactions? Are there recommended R-Tile debug signals for determining why the root port stops after this message? Could an incorrect Flow Control advertisement—especially Completion Header/Data credits—cause this behavior even if InitFC2 completes? Are there known PERST#, cold-boot, or FPGA-configuration timing requirements for enumeration when using PIPE Direct mode? We are currently capturing the following signals: LTSSM state Data Link Layer state InitFC1/InitFC2 and UpdateFC status Received TLP Fmt/Type and complete header Received TLP sequence number LCRC result ACK/NAK request and transmitted ACK/NAK sequence number Replay timer/replay status RX block lock, CDR lock, and lane numbers Raw 1024-bit PIPE RX block data Any guidance on the expected transaction sequence after Set_Slot_Power_Limit, or additional signals that should be captured, would be greatly appreciated. Thank you.
R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work
We recently generated an R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK DEV AGM039EA) with both Quartus Prime Pro 25.3.1 and 26.1. However, the CXL link is always down and stuck at Gen1 2.5Gbps. Do you have any suggestions, or is there a working CXL design example for this kit? We verified that the link functions perfectly with a PCIe Gen5/Gen4 example.We recently generated an R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK DEV AGM039EA) with both Quartus Prime Pro 25.3.1 and 26.1. However, the CXL link is always down and stuck at Gen1 2.5Gbps. Do you have any suggestions, or is there a working CXL design example for this kit? We verified that the link functions perfectly with a PCIe Gen5/Gen4 example.
Cyclone VGT Dev Kit boards - some new boards failing to boot from NOR Flash
We've been using these boards for years, having certified them for use in one of our products. In the last few months we have now received 5 of these boards and they fail to configure from NOR flash. These are all the new Rev B CVGT Dev Kit edition. Not all of the new RevB fail, but the fail rate is high, getting close to 50%. Yes, we know they changed to a Micron NOR flash for Rev B and rerouted some data lines, we are using the new RevB MAX5 files and have updated the Cyclone V NOR flash pins to match as well. I made some diagnostic changes to the MAX5 boot source (I set the PGM leds to count retries) and discovered that on the bad boards, the boot process goes through multiple configuration retries and eventually the watchdog timer fires, turns on the ERR (D5) red LED and stops. With the factory image they come with, there are also dozens of retries, then sometimes the boards fail, sometimes they boot up. With the slow speed that the NOR flash configuration runs at, there is no reason that it should ever fail and retry, and indeed on good boards they configure the first time every time with no retries. The first four we were able to send back to Altera (Via digikey where we bought them). We just got another bad one yesterday, this one from Mouser. Has anyone else seen this issue, and/or heard from Altera about this? Board link: https://docs.altera.com/r/docs/792833/current/cyclone-v-gt-fpga-development-kit-user-guide/kit-featuresARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
Hi Team, We recently purchased license for the ARM DS5 IDE from Altera with License file contains note as NOTICE="For use with Intel or Altera devices only". I am using Arm Development studio IDE with version 2025.1-1. ALtera Agilex 5 FPGA device configured with custom soft macro based design which is only having ARM Cortex M55 processor cores with coresight debug IP . My question is whether ARM DS IDE will detect, access and debug the Cortex M55 cores which is in the fpga through the JTAG USB Blaster ? Please provide the detailed explanation Regards Suresh
JTAG pins order for USB Blaster III - 1.27" header
USB Blaster III header has shrined in size relatively to the previous JTAG cables. I see that in addition, pinout order has changed(according to USB Blaster III user guide). So, if I want to place on a new board that I'm developing a matching connector(pitch=1.27") for USB Blaster III (without using the adapter board from the KIT), then I have to use new pinout order: 1-VCC_TRGET, 2-TMS, 3-GND, 4-TCK, 6-TDO, 7-nTRST, 8-TDI, 9-GND, 10-nPROCRST. This order is different then was used with previous JTAG cables. I couldn't find any reference schematic(also of EVAL KITs) that supports this new JTAG order. I will appreciate if anyone from the forum can confirm my observation. If it's possible that someone can answer me with an existing working reference design with 1.27" connector, I will appreciate it more.
Fitter error in A5ED043AB23AI2V Example design
Hi, I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V. During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually. Could you please help me understand how to resolve this issue?Verifying R-Tile PIPE Direct x8 lane-to-pin mapping on Agilex 7 I-Series Dev Kit
Hi all, I am bringing up a custom PCIe Gen5 controller on the Intel Agilex 7 I-Series Development Kit using the R-Tile Hard IP in PIPE Direct mode (1×16 bundle, only Octet 0 / lanes 0–7 active for now). The soft logic above PIPE (LTSSM, TX TS1/TS2 generation, RX word aligner, 8b/10b decode) is custom RTL. Symptom During Polling.Active, only 2 of 8 lanes ever reach wa_locked = 1 in my soft K28.5-comma word aligner. The other 6 lanes stay in SEARCH/VERIFY indefinitely. The 2 locking lanes are not always the same pair across resets, which makes me suspect either (a) a per-lane CDR / rx_valid gating issue, or (b) a lane-to-pin mapping mismatch between my QSF and the actual PCIe edge connector routing on the dev kit. Before I dig deeper into the CDR / rxdatavalid side, I would like to sanity-check the pin assignments below against the official Agilex 7 I-Series Dev Kit schematic / pin-out, because if lanes are physically swapped vs. what the host RC expects, only the lanes that happen to land on lane 0 (and possibly its mirror) would ever see TS1 ordered sets. Pin assignments in pipe_direct.qsf (Octet 0, lanes 0–7) Signal Pin Signal Pin refclk0 DR68 refclk1 CU68 pin_perst_n CD58 tx_p_out0 / tx_n_out0 DL74 / DH73 rx_p_in0 / rx_n_in0 DE82 / DB83 tx_p_out1 / tx_n_out1 DB77 / DE76 rx_p_in1 / rx_n_in1 CW80 / CT79 tx_p_out2 / tx_n_out2 CW74 / CT73 rx_p_in2 / rx_n_in2 CM82 / CJ83 tx_p_out3 / tx_n_out3 CJ77 / CM76 rx_p_in3 / rx_n_in3 CF80 / CC79 tx_p_out4 / tx_n_out4 CF74 / CC73 rx_p_in4 / rx_n_in4 BY82 / BU83 tx_p_out5 / tx_n_out5 BU77 / BY76 rx_p_in5 / rx_n_in5 BP80 / BL79 tx_p_out6 / tx_n_out6 BP74 / BL73 rx_p_in6 / rx_n_in6 BH82 / BE83 tx_p_out7 / tx_n_out7 BE77 / BH76 rx_p_in7 / rx_n_in7 BB80 / AW79 IO standards: HCSL for refclk0/1, HIGH SPEED DIFFERENTIAL I/O for all TX/RX, 1.0V for pin_perst_n. Lanes 8–15 (Octet 1) are assigned in the QSF as well but are intentionally excluded from the active datapath in this build. Specific questions Are the lane 0–7 TX/RX pin numbers above the correct mapping for the PCIe edge connector on the Agilex 7 I-Series Dev Kit when the R-Tile is configured as a PIPE Direct 1×16 bundle and only the lower octet is used as a x8 link? For PIPE Direct 1×16 with Octet 0 active, is refclk0 (PIN_DR68) the correct refclk source, or does the bundle require both refclk0 and refclk1 driven from the same 100 MHz source even though only 8 lanes are used? Are there any lane-reversal / polarity-inversion considerations on this dev kit that I would need to handle in soft logic vs. inside the R-Tile IP (i.e. does the IP already account for board-level lane reversal so that lane 0 in RTL is guaranteed to be lane 0 at the connector)? Any pointer to the authoritative pin-out table for this board's PCIe edge connector would be very helpful. Thanks!
