New ContributorA question about reading the configuration space of the R-Tile PCIe IP EP
Hello,
Recently, I generated an EP device using the R-Tile PCIe IP, and I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface.
- However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 as 0x002100B0, while the .xlsx file states it is 0x000800B0.
- Shouldn't the PCIe configuration space be 4KB? Why are 16-bit address lines being used to access the configuration space?
- Given that the read data width is 8 bits, does a value of a configuration register (32 bits) need to be read four times to be obtained?
- If I want to know the bus number and device number of the EP device in the user logic, can I directly obtain these from the configuration registers?
Thank you!
Recently, I generated an EP device using the R-Tile PCIe IP. I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 is 0x002100B0, while the .xlsx file states it is 0x000800B0. Additionally, shouldn’t the PCIe configuration space be 4KB? Why are 16-bit address lines used to access the configuration space? Furthermore, if I want to know the bus number and device number of the EP device in the user logic, can I directly obtain them from the configuration registers?
Thank you!
