A question about reading the configuration space of the R-Tile PCIe IP EP

Hi xingyunzhidi

There is a new update to the x16 register map (Revision 4). Please refer to the latest register map here: https://docs.altera.com/v/u/resources/747322/r-tile-avalon-streaming-fpga-ip-for-pci-express-rev.-b-register-map

For the x16 register map, the configuration address for the PF0 MSI‑X Capability Structure Register is 0x00B0.

Thanks.
Best Regards,
Ven