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xingyunzhidi's avatar
xingyunzhidi
Icon for New Contributor rankNew Contributor
1 month ago

A question about reading the configuration space of the R-Tile PCIe IP EP

Hello, Recently, I generated an EP device using the R-Tile PCIe IP, and I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I fo...
Board Debug
Fpga Devkit
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 month ago

Hi xingyunzhidi,

Thank you for your patience.

Please see my responses below to address your questions.
1. I believe you referred to the x16 Register Map. There may be a typo in the Example illustration in the user guide. Please refer to the Register Map excel sheet for the reconfiguration address, i.e. 0x000800B0 for PF0 MSI-X Capability Structure Register.
2. Yes, the PCIe Configuration Space is 4KB per function. 16-bit address is used to support the PFs.
3. Yes, since the readdata is 8 bits wide, you need four times read operations to obtain the 32-bit register value.
4. No. The BDF information is not stored in the PCIe Configuration Space Register. The BDF is managed by the host. You may find bus number information (not the full BDF) in Type 1 Configuration Space Header if you configure the R-Tile PCIe IP to RP. Please refer to the PCIe Base Spec for details.

I hope this addresses your questions. Please let me know if you have any concerns.

Thanks.
Best Regards,
Ven