Stratix 10 FPGA Dev Kit VCCIO_FMC voltage issue
The FMC VCC IO voltage level is adjustable using a resistor on the board as shown below. The default is 1.8V and that works fine. When I depopulate the resistor (R468) to get 1.2V, the output voltage goes to 0V and the enable line for the DC-DC converter also goes low. Any idea what the reason for this is? And what is the fix?
A question about reading the configuration space of the R-Tile PCIe IP EP
Hello, Recently, I generated an EP device using the R-Tile PCIe IP, and I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 as 0x002100B0, while the .xlsx file states it is 0x000800B0. Shouldn't the PCIe configuration space be 4KB? Why are 16-bit address lines being used to access the configuration space? Given that the read data width is 8 bits, does a value of a configuration register (32 bits) need to be read four times to be obtained? If I want to know the bus number and device number of the EP device in the user logic, can I directly obtain these from the configuration registers? Thank you! Recently, I generated an EP device using the R-Tile PCIe IP. I would like to access the configuration space of the EP device through the Hard IP Reconfiguration Interface. However, I found that the addresses of the configuration registers described in the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide do not match those in the rtile-avst-ip-for-pcie-registermap.xlsx. For example, the User Guide mentions the address for the MSI-X Capability Structure for PF0 is 0x002100B0, while the .xlsx file states it is 0x000800B0. Additionally, shouldn’t the PCIe configuration space be 4KB? Why are 16-bit address lines used to access the configuration space? Furthermore, if I want to know the bus number and device number of the EP device in the user logic, can I directly obtain them from the configuration registers? Thank you!
Failed to get MAX10 Triple Speed Ethernet example design to compile
Greetings Altera Experts, I have been trying to recreate an ALTER example design for a MAX 10 Development kit :: "MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide" The problem is that when i read in the max10tse_q_18_0_std.par into a new Quartus project using the same version of Quartus in which the project was originally created from (QUARTUS STD 18.0) it seems to go through initial enumerate and synthesis part OK but then when i try to open the QSYS Platform i see a load of RED errors due to missing components, which are these IP's: st_mux_2_to_1, aso_splitter, error_adapter2, eth_gen, eth_mon So basically most of the QSYS design apart from the TSE and a reset and clock are missing ! I tried to doing the 'upgrade IP' in Quartus for the Qsys component but that didn't help, and also i did a IP library refresh. Again no help. Does anybody got any suggestions please as to how to get these missing IP components ? Or is there a Git rep somewhere with a complete design i can compile for a MAX10 dev board using the Triple Speed Ethernet core ? I have attached the Altera User Guide for this example design to this case. I also added a screenshot showing the errors i get from loading up QSYS. Thanks for any help, Dr Barry H
nCONFIG and nSTATUS,CONF_DONE always LOW EP4CE6
Hello everyone, i has problem about hardware of EP4CE6E22C8, i configure initialize pin like under About power supply, i sure that every bank has right voltage. The problem is when i connected through USB Blaster, quartus cannot detect device, when measure initialize pin, i see voltage in nSTATUS, nCONFIG, CONF_DONE always 0V although 3v3 pull up work. I checked chip solder right, 3v3 work, nSTATUS, nCONFIG, CONF_DONE do not touch GND. What should i do next ? Thanks everyone.MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry H
Does the FPGA N3000 support OpenCL and OneApi?
I received an INTEL FPGA PAC N3000 card, and taking the opportunity, I decided to learn how to develop with SYCL and oneAPI. However, I ran into problems. I fully installed the FPGA PAC N3000 Acceleration Stacks v1.3.1 and also updated the board's BMC from D.1.0.12 to D.2.0.19. Then I started configuring oneAPI 2022 using intel-basekit and fpga-addon, but proper configuration requires bsp, and I couldn't find it anywhere. I also saw that on the website page for Quartus Prime Pro 19.2, which is installed with IAS 1.3.1, there's a tab with oneAPI and BSPs for boards. I looked at other versions, but I only found mentions of Arria 10-GX and Arria 10-SX. I'm not sure if this will help, but the log is from CentOS 7.6.1810. [root@node-fpga ~]# fpgainfo fme Board Management Controller, MAX10 NIOS FW version D.2.0.19 Board Management Controller, MAX10 Build version D.2.0.6 //****** FME ******// Object Id : 0xF300000 PCIe s:b:d.f : 0000:84:00.0 Device Id : 0x0b30 Numa Node : 1 Ports Num : 01 Bitstream Id : 0x23000110010309 Bitstream Version : 0.2.3 Pr Interface Id : f3c99413-5081-4aad-bced-07eb84a6d0bb Boot Page : user [root@node-fpga ~]# fpgainfo bmc Board Management Controller, MAX10 NIOS FW version D.2.0.19 Board Management Controller, MAX10 Build version D.2.0.6 //****** BMC SENSORS ******// Object Id : 0xF300000 PCIe s:b:d.f : 0000:84:00.0 Device Id : 0x0b30 Numa Node : 1 Ports Num : 01 Bitstream Id : 0x23000110010309 Bitstream Version : 0.2.3 Pr Interface Id : f3c99413-5081-4aad-bced-07eb84a6d0bb ( 1) Board Power : 59.65 Watts ( 2) 12V Backplane Current : 2.91 Amps ( 3) 12V Backplane Voltage : 11.92 Volts ( 4) 1.2V Voltage : 1.20 Volts ( 6) 1.8V Voltage : 1.80 Volts ( 8) 3.3V Voltage : 3.27 Volts (10) FPGA Core Voltage : 0.90 Volts (11) FPGA Core Current : 14.47 Amps (12) FPGA Core Temperature : 62.50 Celsius (13) Board Temperature : 42.00 Celsius (14) QSFP A Voltage : N/A (15) QSFP A Temperature : N/A (24) 12V AUX Current : 2.08 Amps (25) 12V AUX Voltage : 11.97 Volts (37) QSFP B Voltage : N/A (38) QSFP B Temperature : N/A (44) Retimer A Core Temperature : 63.00 Celsius (45) Retimer A Serdes Temperature : 64.00 Celsius (46) Retimer B Core Temperature : 0.00 Celsius (47) Retimer B Serdes Temperature : 0.00 Celsius [root@node-fpga ~]# aoc -list-boards Board list: pac_a10 (default) Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac pac_s10 Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_s10sx_pac pac_s10_usm Board Package: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_s10sx_pac Memories: device, host [root@node-fpga ~]# aocl list-devices -------------------------------------------------------------------- Device Name: acl0 BSP Install Location: /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac Vendor: Intel Corp Physical Dev Name Status Information pac_f200000 Uninitialized OpenCL BSP not loaded. Must load BSP using command: 'aocl program <device_name> <aocx_file>' before running OpenCL programs using this device DIAGNOSTIC_PASSED -------------------------------------------------------------------- [root@node-fpga ~]# aocl initialize acl0 pac_a10 aocl initialize: Running initialize from /opt/intel/oneapi/compiler/2022.2.1/linux/lib/oclfpga/board/intel_a10gx_pac/linux64/libexec bitstream.c:391:validate_bitstream_metadata() **ERROR** : Interface ID check failed Error writing bitstream to FPGA: invalid parameter Error programming device aocl initialize: Program failed. [root@node-fpga ~]#
EPM9320LI84-20
Hello! Could you please clarify something? Within the same batch of EPM9320LI84-20 FPGAs, the marking quality varies significantly, which is especially noticeable in the letter A in the ALTERA logo. This is not an isolated case within the batch—there are several chips with the same issue. Could this happen during manufacturing? As you understand, these chips were discontinued long ago and are no longer available from official distributors, so we have to source them from less reliable suppliers. Please respond as soon as possible. Thank you!
Process for RMA - Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Hello there, I have an Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (https://www.altera.com/products/devkit/a1jui0000049utomam/agilex-7-fpga-i-series-transceiver-development-kit-6x-f-tile) that has recently stopped functioning correctly. In particular, the JTAG chain does recognize the existence of the Agilex FPGA. Quartus's JTAG debugger throws an error: Error: TDI connection to the first detected device 10M16S(A|C|L) might be shorted to GND Error: The TCK and TMS connections to the device before the first detected device 10M16S(A|C|L) might have a problem Info: Detected 1 device(s) Info: Device 1: 10M16S(A|C|L) When trying different settings on the JTAG chain selection mux, it is clear that the System MAX10 is detected and functioning correctly, but the Agilex FPGA cannot be detected. We have tried to reprogram the MAX10 with the factory default image, but there has been no change. We suspect a hardware issue with the JTAG chain. At this point, the Agilex FPGA is not accesible, rendering the board unusable for our purpose. Could ALTERA please support us on this? Is it possible to start the process for an RMA? Are there any options that we can consider? We greatly appreciate your assistance in this time of need Thank you
Arria 10 boot from MT25QU01G device failure
Hello , I have a development board which consists of two arria 10 devices that retrieve the configuration from a MICRON MT25QU01G device . Although through the usb blaster seems that i can access the memory using JTAG and SFL and successfully write data in the memory , when the two arria devices boot it seems that there is a configuration error. As referred to the datasheet the first arria is configured in active serial configuration scheme by selecting the appropriate MSEL pins while the other in passive serial . I have also tied the nCONFIG, nSTATUS , DCLK , (AS_DATA_0 and AS_DATA_1) and CONF DONE as referred in pin connection and guidelines. Do you know why the FPGAs are not configured properly ? Regards Manolis
