Agilex 7 interface with DDR4
Hi experts, I am using Agilex 7 (AGFB022R25A2I3V). I wish to use the internal bridges to write to and read from DDR4. My idea is like this,... Build a internal connections using Platform Designer in Quartus Prime Pro. Then generate the Avalon-mm addresses of the DDR4. At the Linux driver / application code, we write C program to write to and read from the specific address of the DDR4. Do you know where I can find such sample project? I have been trying to search for months yet still can't find it. I have gone through a lot of intel documents and video clips. Yet still they can't help. I am still not successful in implementing my requirement. Could you please help? Regards
Custom linux image build failure for Arri10 SoC development kit
Hi, I am following the below documentation to build my custom Linux image for Arria10 SoC development kit. While building Yocto Rootfs, I am facing oe_runmake error. I have attached the log as well. This is happening in the build process while compiling linux-socfpga-6.6+git package. I tried below steps as well step-1: bitbake -c cleanall linux-socfpga step-2: bitbake linux-socfpga But at step-2, again same issues. Any help would be appreciated. Thanks, Sai
Power up the device(CYCLONE 5) in temperature under zero
we are using in our board the device CYCLONE 5 - 5CSEBA5U23, when we are trying to power up the device in temperature under zero( -5 cel), we are getting the " altera_load" failed with error code -2" and the "conf_done" stays low. If the board is power up in a positive temperature , and we are cooling the board, the device working fine. We check all signals control , the are setting ok.
Cyclone 5 first boot linux crashes, howto debug?
Hello, We have a design with a Cyclone V FPGA. Some boards only boot after a reset following power-on. Problem: The Debian Linux with U-Boot boots from the SD card, but after approximately 10 seconds, the system crashes and becomes unresponsive. The login prompt appears (on UART debug), but I cannot enter anything, and the network interface does not work. How should I start troubleshooting? There is a JTAG on the board, but I have never used it until now. Any hints or links would be greatly appreciated. Sorry, but I have no idea how to resolve this, or where to start with the troubleshooting.
Intel® FPGA Technical Training for every public users
Dear all, Altera FPGA technical training offers many ways to learn. Sharpen your FPGA design skills today! All public training is free to attend. Training includes: Instructor-led Classes On-Demand eLearning Webinars and Workshops Quick Videos and many more Certified Intel FPGA Training Partners are available to teach in the following regions of the world: Africa, Asia, Australia and New Zealand, Europe, India, Israel, and South America. Click here Altera® FPGA Technical Training for more details. Kind regards, Altera Support Team
Stratix 10 MCDMA host: Queue reset failed
Hello, I have been trying to get an MCDMA example design working on a Stratix 10 MX device (1SM21BEU2F55E2VG). You can consider me a beginner with the Intel FPGAs. The project details are as follows. Device side ----------------- Project: Platform designer project with H-tile PCIe MCDMA with AVMM interface. PCIe configuration - Gen3x16 512-bit interface, 250 MHz No of PFs - 1 Everything else is set to default, as this is a slightly modified version of the basic example design generated by Quartus. refclk - connected to differential PCIe clock PCIE_REFCLK_P and PCIE_REFCLK_N pin_perst - connected to PCIe PERST# npor - tied to 1 in the top level wrapper Verilog module xcvr - PCIe interface The top-level wrapper only instantiates this, sets npor to 1, and passes every other signals. The hip_ctrl and hip_pipe are left unconnected in the wrapper. The design compiles properly, and the sof file can be programmed without error. ----------------------- Host side ----------------------- On the host side, I followed the steps mentioned in the MCDMA example user guide. https://www.intel.com/content/www/us/en/docs/programmable/683517/23-4/introduction.html The device is listed the lspci output and shows up the BAR regions. However, when I try to run any of the test programs in the software/user/cli, nothing runs successfully (this driver and user utilities/examples are also generated as part of the example MCDMA project). Most of the time the error is "Queue reset failed" or the programs hang without any output. Reading device memory via the supplied devmem utility always returns 0xFFFFFFFF. My guess is something wrong with the reset logic/process, however I am unable to fix it so far and it feels like I am missing something obvious. Any lead in this regard would be helpful. Let me know if you need more information in this context. Thanks and regards, Arnab
Altera USB Blaster (usb-0)
Hi all, i have a device which used fpga cyclone v 5CEBA4U15C7, iam using quartus prime lite 19.1, my goal is to access this fpga device through a jtag connection (connections are done) and flash sof files and view how the fpga works, The altera usb blaster iam having is altera usb blaster (not usb blaster ii, in programmer the hardware will show this device as USB-0). This usb blaster is not recognizing my fpga, instead, it is showing 5ceba4, the exact part number is not showing, and iam not able to flash my sof files, even if i selec 5ceba4 and flash via jtag, programmer will show that it's failed, should i get a usb blaster ii ? in the data sheet of usb blaster (USB-0) it is shown that it supports cyclone V EPCQ-L devices, in the data sheet of usb- blaster (USB-II) it is shown that it supports Cyclone v FPga devices, i just wanted to confirm whether this is due to usb-0 not supporting my exact fpga board, or should i get usb-ii for accessing my exact fpga device. Thanks in advance, mahesh. this is how usb blaster is shown in device manager.
Why does aoc set ii to 6 when I use high clock frequencies?
I have a simple toy that I want to run at 1000 MHz kernel that doesn't do much: __attribute__((uses_global_work_offset(0))) __attribute__((max_global_work_dim(0))) __kernel void netsim( __global const volatile float * restrict gl_vm ) { float vm[50000]; #pragma ii 1 #pragma ivdep #pragma speculated_iterations 64 for (int i = 0; i < 50000; i++) { vm[i] = gl_vm[i]; } } According to the report (see screenshot), II=6 and latency=927. Why can't the compiler lower the latency and set II to 1 here?
