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sumanthraju's avatar
sumanthraju
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3 months ago

Fitter error in A5ED043AB23AI2V Example design

Hi,

I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V.

During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually.

Could you please help me understand how to resolve this issue?

 

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Fpga Devkit
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soc devkit

6 Replies

  • RongY_altera's avatar
    RongY_altera
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    2 months ago

    Hi,

    Are you putting PCIe and USB3.1 on the same bank? using one XCVR?

    Do they share the same clock source?

     

    Regards,

    Rong

     

  • sumanthraju's avatar
    sumanthraju
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    2 months ago

    hi,

    Pcie using  4A,4B,4C banks. 

    USB3.1 bank is 1C,5A bank. for this A5ED043AB23AI2V , 12 XCVR  are available.

     

    can you please hlep me to ressolve the fitter error

     

  • sumanthraju's avatar
    sumanthraju
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    2 months ago

    Hi,

    Thank you for your reply.

    I am trying to use the same pin assignment as the DEV KIT A5ED065BB32AE4SR0 design. However, while compiling for the A5ED043AB23AI2V package, I am getting fitter errors.

    Could you please help us resolve the compilation issue, or alternatively provide a compiled QAR file for enabling PCIe Gen4 + USB3.1 support in the A5ED043AB23AI2V package?

    Waiting for your prompt response.