Regarding data for the Altera Arria V GX FPGA development kit
I am looking for information on an Altera Arria V evaluation board that is equipped with the SFP module. I think that Arria V GX FPGA Development Kit is the relevant product. However, when I check the links below, I see “Error 404: Page Not Found.” Are the following links incorrect? Arria V GX FPGA Development Board Reference Manual (English, PDF) http://www.altera.com/literature/manual/rm_avgx_fpga_dev_board.pdf Arria V GX FPGA Development Kit User Guide (English, PDF) http://www.altera.com/literature/ug/ug_avgx_fpga_dev_kit.pdf Kit installer ftp://ftp.altera.com/outgoing/devkit/12.0/arriaVGX_5agxfb3hf40es_fpga_v12.0.0.exe Please provide the correct links. Best regards, Hachiware.
LLM Implementation on Agilex 5 E-Series 065B Modular Dev Kit
I am currently working on deploying Large Language Model (LLM) inference using FPGA AI Suite on the Agilex 5 E-Series 065B Modular Development Kit. I have two clear and specific questions: Is the Agilex 5 E-Series 065B officially supported for LLM / Transformer inference with FPGA AI Suite? Is the following workflow officially supported for LLM inference on this board? Step 1: Export a pre-trained LLM from Hugging Face to OpenVINO IR format using optimum-intel Step 2: Generate the target FPGA architecture file using architecture_optimizer for Agilex 5. Step 3: Compile the OpenVINO IR model for the FPGA using: • dla_compiler → for Sequential flow, or • Spatial Compiler → for Spatial flow. Step 4: Integrate the generated FPGA AI Suite IP into a Quartus Prime project, generate the bitstream, and program it onto the Agilex 5 E-Series 065B board. Step 5: Run inference using the FPGA AI Suite runtime (host application). I understand this may not be a push-button process and could require significant modifications to the generated RTL — but is this workflow still considered a viable starting point for implementing LLM / Transformer inference on the Agilex 5 E-Series 065B? Thank you.
Fitter error in A5ED043AB23AI2V Example design
Hi, I have tried using the example design of the A5ED065BB32AE4SR0 development kit and modified the part number to A5ED043AB23AI2V. During compilation, I am encountering a fitter error when both PCIe and USB 3.1 are enabled together. However, I am able to compile successfully when using each interface individually. Could you please help me understand how to resolve this issue?Example design for [MAX 10 User Flash Memory (UFM) Data Incrementing Burst Read Mode].
Hello. Thank you for your help. I would like a example design for [MAX 10 User Flash Memory (UFM) Data Incrementing Burst Read Mode]. https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset03/max10ufm-incrementing-burst-read-ug.pdf However, I cannot find the design website link referenced in this document. Please provide the design described in this document. Additionally, the following link does not contain MAX 10 Example Designs. Please provide a website link that contains all MAX 10 Example Designs. https://altera-fpga.github.io/rel-26.1/ed-demo-list/ed-list/ Best regards, Hachiware
Mandelbrot viewer on Cyclone V - Platform Designer layout
Hello, I’ve been trying to implement on my DE1-SoC an outstanding Mandelbrot Viewer written by 3 fellows at Cornell, which published partial information in an online available final report I manage to compile the C++ code and perform a sanity check on my x86 host: And I manage to compile the C++ to run on the DE1-SoC HPS: Also, I got Quartus to compile the Verilog provided in the report, though it’s not in its final, working form. I’m pretty sure my problem is in the Platform Designer (formerly Qsys) layout. Been trying many variations around this layout for several weeks, but with no success: I chose the components to my best understanding based the report, that mentions: "The communication between the FPGA and the hard processor system happens over a memory-mapped AXI bus. Requests for tiles are placed into a FIFO on the FPGA, and solved tile data is written out into external SDRAM memory. Requests from the HPS are sent over the AXI bus into a FIFO located on the FPGA. A request distributor then pulls the message off of the FIFO using the avalon streaming interface and handles it. (I assume this is with reference to request_distributor.sv attached in report) As the solvers solve pixels of the output tile, they write the results to SDRAM. Arbitration logic collects results from any solvers which are ready to write. (I assume this is with reference to write_arbitrator.sv attached in report)" Additional info: To my understanding, a top module (not attached to the report) is probably instantiating a multi_tile_solver.sv module and a module from Platform Designer, nothing more. As can be seen in the files in the report, multi_tile_solver.sv instantiates a request_distributor.sv module, a write_arbitrator.sv module, and NUM_SOLVERS tile_solver_legit.sv modules. Each tile_solver_legit.sv instantiates a solver.v, which instantiates a solver_control.v and a solver_datapath.v. It uses on-chip SRAM in the form of M10K block, which are created from the verilog source code, rather than having anything to do with the Platform Designer layout. I think I’m pretty close to running this amazing project, yet have been stuck on this platform designer layout and don’t succeed in finalizing. Any help would be much appreciated.
Available replacement for the discontinued P/N: MK-A5E065BB32AES1 ?
Hello, PDN: https://www.mouser.com/PCN/Intel_Corporation_PDN2513.pdf?srsltid=AfmBOoqEg4CcKdQVpDMH8g2nQDlihxYoQoJwu3Bcg91PBuKx__G1W-Mf is suggesting P/N: MK-A5E065BB32AEA (Future) as replacement for the already discontinued P/N: MK-A5E065BB32AES1 A customer is desperately searching for this old or the new board, or an alternative that would be immediately available for an important project. His previous order was not considered any more, unfortunately. Can you possibly help to get hold of one of these boards, or would you know a reseller who might still have stock? Thank you very much Best regards Adnan (ref: Q1CDFE8)MAX10 10M50 Development KIT Triple Speed Ethernet problem
Greetings to all of the ALTERA Experts, I have been trying to get a Gigabit Ethernet interface working on an ALTERA MAX10 10M50-C Development kit and keep hitting a bit of a brick wall when tying to communicate with the MARVEL ALASKA 88E1111 PHY. It does not appear to respond correctly when i try to read for example the PHY ID register (address x02) which should respond with the value 0x041 but instead sends back 0x7fff. I am using a System Verilog HDL approach to both instantiate the ALTERA Triple speed IP core in MAC only mode, with 2K word FIFOs, and full duplex 10/100/1000. The IP is set to work in Gigabit mode. When i connect the board to a windows 10 PC using an Ethernet cable i can see the Yellow LED lit up on the Dev KITS PHY connector and when i test the connection on the windows 10 PC it says it is up and connected. But when i try to send any Ethernet packets (i am using IPV4 + UDP as packet payload) nothing gets through to the PC. I have verified this as well using WIRESHARK which shows me no ethernet frames are coming in from the MAX10 Dev kits end. I have set the Triple speed Ethernet IP cores mac0/mac1 register to this random value: 48'h321C23174ACB I think this is OK and what the Triple Speed Ethernet User Guide says. Please correct me if my thinking is wrong though ? Questions: a) Does any body know of any errata / bugs with this Development KIT OR with the MARVELL PHY ? b) Can anybody point me to a Git Hub which has a known working example using this ALTERA Dev Kit along with this MARVELL PHY ? This can use either a HDL approach (like i am trying to use here) or a NIOSV softcore processor approach. c) The MAX10 Dev Kit has 2 Ethernet PHYS. A and B. I think that the MAX10 10M50-C Dev Kit sets its A MARVELL PHY Address to 0x0 and its B side MARVELL PHY Address to 0x1 BUT its not easy i found to figure out the PHY addresses. If somebody can please show me how to properly derive the PHY ADDRESSES for both the MARVELL 88E1111 devices for PHY A (ETHERNET A) and PHY B (ETHERNET B) on the MAX10 10M50-C Dev Kit Board Schematic) i will be very grateful ! Thanks for any help, Dr Barry HRegarding Quartus Prime License Activation for the Agilex 5 Evaluation Kit
Does the Agilex 5 Premium Development Kit include a one‑year paid Quartus Prime license? The product brief states that it is included, but I would like to confirm. https://docs.altera.com/v/u/docs/815177/agilextm-5-fpga-e-series-065b-premium-fpga-development-kit-product-brief If the license is included: ・Is the same one‑year license also provided with the Modular Development Kit? ・Does the bundled license also include the IP Base Suite, as with a standard paid Quartus Prime license?Failed to get MAX10 Triple Speed Ethernet example design to compile
Greetings Altera Experts, I have been trying to recreate an ALTER example design for a MAX 10 Development kit :: "MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide" The problem is that when i read in the max10tse_q_18_0_std.par into a new Quartus project using the same version of Quartus in which the project was originally created from (QUARTUS STD 18.0) it seems to go through initial enumerate and synthesis part OK but then when i try to open the QSYS Platform i see a load of RED errors due to missing components, which are these IP's: st_mux_2_to_1, aso_splitter, error_adapter2, eth_gen, eth_mon So basically most of the QSYS design apart from the TSE and a reset and clock are missing ! I tried to doing the 'upgrade IP' in Quartus for the Qsys component but that didn't help, and also i did a IP library refresh. Again no help. Does anybody got any suggestions please as to how to get these missing IP components ? Or is there a Git rep somewhere with a complete design i can compile for a MAX10 dev board using the Triple Speed Ethernet core ? I have attached the Altera User Guide for this example design to this case. I also added a screenshot showing the errors i get from loading up QSYS. Thanks for any help, Dr Barry H
