Mandelbrot viewer on Cyclone V - Platform Designer layout

Thank you very much for your response. 

I’m trying to implement what you’re saying as components and wiring.

1. You mentioned:

connect the "Avalon Memory Map Slave" of the FIFO IP to any of the H2F axi masters.

I’ll be using the full AXI bus (not the lightweight), so does your sentence mean that I should wire the Avalon FIFO Memory Intel FPGA IP → “in” interface, of type Avalon MM Slave to the h2f_axi_master interface of the hps0 component like shown below? What about in_csr and other interfaces of the FIFO?

If the answer is yes, is this the interface I should match 0xC000_0000 to? The HPS side code does refer to this address. I guess not fifo_0.in, be cause i get the error:
Error: prelim_qsys.hps_0.h2f_axi_master: fifo_0.in (0xc0000000..0xc0000007) is outside the master's address range (0x0..0x3fffffff).

2. Still regarding the HPS → FPGA path through the FIFO, it’s stated that the verilog does the following: "A module named “request distributor” pulls the message off of the FIFO using the Avalon streaming interface and handles it." Can you please relate to how the Avalon streaming interface should be used here? Which IP should I add on Platform Designer? I’ll mention that this “request distributor” module has input signals: “in_data”, “in_valid”, “in_end_of_stream”, which suggest a streaming interface rather than a memory mapped interface. When I searched in the catalog, these are the results that came up, and I don’t know which one I should be using, if at all:

The only other thing I could think of is adding a custom component and under “Signals and Interfaces” add “Avalon Streaming Source” and “Avalon Streaming Sink” interfaces manually, but that doesn’t seem right. And even if I did, I don’t know how its interfaces should be wired:

The GUI will only let me alternate the "avalon_streaming_sink" interface of type "Avalon Streaming Sink" between the same component's "avalon_streaming_source" interface of type "Avalon Streaming Source":

or the "out" interface of type "Avalon Streaming Source" in the fifo_0 component:

but not both at the same time.

3. Regarding FPGA→HPS, you mentioned:

Then you can retrieve values from the SD RAM using the same mechanism

Can you please help me understand how to turn this to Platform Designer components and wiring? I’ll mention that the verilog module that’s in charge for the “writing arbitration” has output lines (of SystemVerilog’s type logic): “out_data”, “out_address”, “out_write_en”. I’m assuming that there should be some component that should be connected in the gui to the f2h_axi_slave interface of the hps component?

Thank you very much for your  help

Thank you very much for your replies and assistance. I think I might be getting closer.

A big part of what I'm trying to find out but didn't manage to, is whether or not a custom component is even needed. I'm writing again all of the communication that has to be done:

HPS --> FPGA: FIFO, and then messages "pulling" off of the FIFO using the avalon streaming interface

FPGA --> HPS: SDRAM (which is external to the FPGA).

1. In the most general case, to implement this kind of communication, does this necessarily require a custom module that has the verilog source file/files included in it?

from what I understand from the workflow, there are two methods when working with Platform Designer: the first one, which is the one I thought was more common, is to make the layout wiring and address mapping in the gui, export conduits, and then use the auto generated code to tie these conduits to logic in the verilog source code.

the second one, which i'm less familiar with and trying to understand if necessary in this case, is creating a new custom component add adding files to it, use the "analyze synthsis files" and make the gui wiring.

2. Addition information: it's mentioned that: "The FIFO instantiated on the FPGA, along with the Avalon bus structure and SDRAM controller that we used, were all Altera". I take this as supporting the first kind of workflow - without a custom component. Does this make sense? if so, please help me figure out the layout, because I've really been trying all my best and couldn't figure it out for several weeks. 

In order to add a SDRAM controller, i went to an older quartus version (20.1 because the SDRAM Controller Intel FPGA IP seems to no longer be supported with 24.1 and doesn't appear in the catalog):

Please note that:

 the "out" interface of the fifo couldn't be wired to anything in the screenshot above if there was no sink in the entire design to accept it. So what I did, is add a new custom component but only because i didn't know what altera IP i should use. As I explained above, when searching in the catalog, i didn't find the right thing, maybe i'm wrong? attaching again:

all the options below, which were cut out from the screenshot, are non standard too.

 This "custom component" of mine has nothing to do with my verilog source code, no files added in it. It only includes simple three interfaces: clock, reset and avalon_streaming_sink:

in order to accept the fifo_0.out source.

3. Do you think that the platform designer layout shown above should be sufficient to implement the communication of the problem described in the beginning of this message? what do i need to know about setting the base address and span of the SDRAM Controller component as a slave on the h2f axi master?

Thank you very much