Mandelbrot viewer on Cyclone V - Platform Designer layout

Thank you very much for your replies and assistance. I think I might be getting closer.

A big part of what I'm trying to find out but didn't manage to, is whether or not a custom component is even needed. I'm writing again all of the communication that has to be done:

HPS --> FPGA: FIFO, and then messages "pulling" off of the FIFO using the avalon streaming interface

FPGA --> HPS: SDRAM (which is external to the FPGA).

1. In the most general case, to implement this kind of communication, does this necessarily require a custom module that has the verilog source file/files included in it?

from what I understand from the workflow, there are two methods when working with Platform Designer: the first one, which is the one I thought was more common, is to make the layout wiring and address mapping in the gui, export conduits, and then use the auto generated code to tie these conduits to logic in the verilog source code.

the second one, which i'm less familiar with and trying to understand if necessary in this case, is creating a new custom component add adding files to it, use the "analyze synthsis files" and make the gui wiring.

2. Addition information: it's mentioned that: "The FIFO instantiated on the FPGA, along with the Avalon bus structure and SDRAM controller that we used, were all Altera". I take this as supporting the first kind of workflow - without a custom component. Does this make sense? if so, please help me figure out the layout, because I've really been trying all my best and couldn't figure it out for several weeks. 

In order to add a SDRAM controller, i went to an older quartus version (20.1 because the SDRAM Controller Intel FPGA IP seems to no longer be supported with 24.1 and doesn't appear in the catalog):

Please note that:

 the "out" interface of the fifo couldn't be wired to anything in the screenshot above if there was no sink in the entire design to accept it. So what I did, is add a new custom component but only because i didn't know what altera IP i should use. As I explained above, when searching in the catalog, i didn't find the right thing, maybe i'm wrong? attaching again:

all the options below, which were cut out from the screenshot, are non standard too.

 This "custom component" of mine has nothing to do with my verilog source code, no files added in it. It only includes simple three interfaces: clock, reset and avalon_streaming_sink:

in order to accept the fifo_0.out source.

3. Do you think that the platform designer layout shown above should be sufficient to implement the communication of the problem described in the beginning of this message? what do i need to know about setting the base address and span of the SDRAM Controller component as a slave on the h2f axi master?

Thank you very much