New ContributorVerifying R-Tile PIPE Direct x8 lane-to-pin mapping on Agilex 7 I-Series Dev Kit
Hi all,
I am bringing up a custom PCIe Gen5 controller on the Intel Agilex 7 I-Series Development Kit using the R-Tile Hard IP in PIPE Direct mode (1×16 bundle, only Octet 0 / lanes 0–7 active for now). The soft logic above PIPE (LTSSM, TX TS1/TS2 generation, RX word aligner, 8b/10b decode) is custom RTL.
Symptom During Polling.Active, only 2 of 8 lanes ever reach wa_locked = 1 in my soft K28.5-comma word aligner. The other 6 lanes stay in SEARCH/VERIFY indefinitely. The 2 locking lanes are not always the same pair across resets, which makes me suspect either (a) a per-lane CDR / rx_valid gating issue, or (b) a lane-to-pin mapping mismatch between my QSF and the actual PCIe edge connector routing on the dev kit.
Before I dig deeper into the CDR / rxdatavalid side, I would like to sanity-check the pin assignments below against the official Agilex 7 I-Series Dev Kit schematic / pin-out, because if lanes are physically swapped vs. what the host RC expects, only the lanes that happen to land on lane 0 (and possibly its mirror) would ever see TS1 ordered sets.
Pin assignments in pipe_direct.qsf (Octet 0, lanes 0–7)
| Signal | Pin | Signal | Pin |
|---|---|---|---|
| refclk0 | DR68 | refclk1 | CU68 |
| pin_perst_n | CD58 | ||
| tx_p_out0 / tx_n_out0 | DL74 / DH73 | rx_p_in0 / rx_n_in0 | DE82 / DB83 |
| tx_p_out1 / tx_n_out1 | DB77 / DE76 | rx_p_in1 / rx_n_in1 | CW80 / CT79 |
| tx_p_out2 / tx_n_out2 | CW74 / CT73 | rx_p_in2 / rx_n_in2 | CM82 / CJ83 |
| tx_p_out3 / tx_n_out3 | CJ77 / CM76 | rx_p_in3 / rx_n_in3 | CF80 / CC79 |
| tx_p_out4 / tx_n_out4 | CF74 / CC73 | rx_p_in4 / rx_n_in4 | BY82 / BU83 |
| tx_p_out5 / tx_n_out5 | BU77 / BY76 | rx_p_in5 / rx_n_in5 | BP80 / BL79 |
| tx_p_out6 / tx_n_out6 | BP74 / BL73 | rx_p_in6 / rx_n_in6 | BH82 / BE83 |
| tx_p_out7 / tx_n_out7 | BE77 / BH76 | rx_p_in7 / rx_n_in7 | BB80 / AW79 |
IO standards: HCSL for refclk0/1, HIGH SPEED DIFFERENTIAL I/O for all TX/RX, 1.0V for pin_perst_n.
Lanes 8–15 (Octet 1) are assigned in the QSF as well but are intentionally excluded from the active datapath in this build.
Specific questions
- Are the lane 0–7 TX/RX pin numbers above the correct mapping for the PCIe edge connector on the Agilex 7 I-Series Dev Kit when the R-Tile is configured as a PIPE Direct 1×16 bundle and only the lower octet is used as a x8 link?
- For PIPE Direct 1×16 with Octet 0 active, is refclk0 (PIN_DR68) the correct refclk source, or does the bundle require both refclk0 and refclk1 driven from the same 100 MHz source even though only 8 lanes are used?
- Are there any lane-reversal / polarity-inversion considerations on this dev kit that I would need to handle in soft logic vs. inside the R-Tile IP (i.e. does the IP already account for board-level lane reversal so that lane 0 in RTL is guaranteed to be lane 0 at the connector)?
Any pointer to the authoritative pin-out table for this board's PCIe edge connector would be very helpful.
Thanks!
