New Contributor
New ContributorHello Fred_Barkins, this is seems to be an specific project not supported directly by Altera, hence the best suggestion could be to make contact with the creator for especifics.
However, we can help you understanding the communication between the HPS (Hard Processor System) and the communication with an FPGA soft device. It seems to me that your program wants to write "tiles into a FIFO". For this you have to connect the "Avalon Memory Map Slave" of the FIFO IP to any of the H2F axi masters. The using memory map addressing, making sure you have the correct address.
Pleasee see:
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html and
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html
and note the values "hps2fpgaslaves" and "lwfpgaslaves"
If you use "FPGA Slaves Accessed Via HPS2FPGA AXI Bridge" then your device address would be 0xC0000000 + <device_address>.
Then you can retrieve values from the SD RAM using the same mechanism
New ContributorThank you very much for your response.
I’m trying to implement what you’re saying as components and wiring.
connect the "Avalon Memory Map Slave" of the FIFO IP to any of the H2F axi masters.
I’ll be using the full AXI bus (not the lightweight), so does your sentence mean that I should wire the Avalon FIFO Memory Intel FPGA IP → “in” interface, of type Avalon MM Slave to the h2f_axi_master interface of the hps0 component like shown below? What about in_csr and other interfaces of the FIFO?
If the answer is yes, is this the interface I should match 0xC000_0000 to? The HPS side code does refer to this address. I guess not fifo_0.in, be cause i get the error:
Error: prelim_qsys.hps_0.h2f_axi_master: fifo_0.in (0xc0000000..0xc0000007) is outside the master's address range (0x0..0x3fffffff).
2. Still regarding the HPS → FPGA path through the FIFO, it’s stated that the verilog does the following: "A module named “request distributor” pulls the message off of the FIFO using the Avalon streaming interface and handles it." Can you please relate to how the Avalon streaming interface should be used here? Which IP should I add on Platform Designer? I’ll mention that this “request distributor” module has input signals: “in_data”, “in_valid”, “in_end_of_stream”, which suggest a streaming interface rather than a memory mapped interface. When I searched in the catalog, these are the results that came up, and I don’t know which one I should be using, if at all:
The only other thing I could think of is adding a custom component and under “Signals and Interfaces” add “Avalon Streaming Source” and “Avalon Streaming Sink” interfaces manually, but that doesn’t seem right. And even if I did, I don’t know how its interfaces should be wired:
The GUI will only let me alternate the "avalon_streaming_sink" interface of type "Avalon Streaming Sink" between the same component's "avalon_streaming_source" interface of type "Avalon Streaming Source":
or the "out" interface of type "Avalon Streaming Source" in the fifo_0 component:
but not both at the same time.
3. Regarding FPGA→HPS, you mentioned:
Then you can retrieve values from the SD RAM using the same mechanism
Can you please help me understand how to turn this to Platform Designer components and wiring? I’ll mention that the verilog module that’s in charge for the “writing arbitration” has output lines (of SystemVerilog’s type logic): “out_data”, “out_address”, “out_write_en”. I’m assuming that there should be some component that should be connected in the gui to the f2h_axi_slave interface of the hps component?
Thank you very much for your help
