Agilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)
Device: A5ED013BB32AE4SCS Quartus Prime Pro 25.1.1 Build 125 I am trying to reconfigure a standalone fabric IOPLL at runtime using the EMIF Calibration IP (emif_io96b_cal), following the HSIO reconfiguration flow described in the Clocking and PLL User Guide (813671), section 6.1/6.4, and the approach discussed in this thread: Agilex 5 reconfigurable PLL - emif | Altera Community - 122952 Setup: - ps_pll: Intel IOPLL FPGA IP, "Enable dynamic reconfiguration of PLL using Calibration IP" = true, IOPLL Type = "I/O Bank" (only selectable value in the GUI), 50 MHz reference clock. - EMIF Calibration IP (emif_io96b_cal), INSTANCE_ID = 0, NUM_CALBUS_PLLS = 1, NUM_CALBUS_PERIPHS = 0, AXI4-Lite subordinate port in FABRIC mode. - pll_calbus / pll_calbus_readdata wired directly between the two IPs. The Fitter fails during the very first placement/plan stage with: Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Error(175001): The Fitter cannot place 1 IOPLL, which is within IOPLL FPGA IP ps_pll_altera_iopll_2000_ihvozry. Error(16234): No legal location could be found out of 11 considered location(s). Error(175005): Could not find a location with: HVIO_IOPLL (6 locations affected) Error(175008): Location was not in the legal region (5 locations affected) I isolated this down to a minimal reproduction: 1) A plain, non-reconfigurable IOPLL alone: places fine. 2) The same IOPLL with calbus reconfiguration enabled, standalone (no EMIF IP at all): places fine. 3) The EMIF Calibration IP alone, calbus tied off, unconnected to any PLL: places fine. 4) The reconfigurable IOPLL and EMIF Calibration IP both present in the same design but NOT wired together (calbus tied off independently on each side): places fine. 5) The reconfigurable IOPLL wired to the EMIF Calibration IP via calbus (the actual intended configuration): fails with the error above, 100% reproducible, regardless of I/O pin location assignments (confirmed by removing every pin constraint from the design entirely - identical error, identical 6+5 location breakdown). I have also tried, with no change to the error: - Removing all pin location assignments (refclk, PLL outputs, etc.) - Setting PLL_REFCLK_INPUT_TYPE to NOT_BALANCED on the IOPLL instance - Quartus Interface Planner tool - "Update Plan" fails immediately with the identical underlying Fitter conflict, before it can even display a plan. Can someone from Intel/Altera help me understand what is actually driving this placement conflict and how to resolve it? Happy to share the minimal reproduction project if useful.Intermittent DE10-Standard error starting GDB server with quartus_hps
Hello, We have 15 DE10-Standard boards being used with Quartus 18.1 and the associated version of Altera Monitor Program on Ubuntu 24.04 (amd64). Generally the boards work without issue, however in the Monitor Program we occasionally see 'Download System - Partial Success: The system has successfully downloaded onto the board, but HPS components could not be configured.' Power cycling the board doesn't seem to resolve the error, nor does swapping the board to a different desktop. After a number of tries the error will go away. We haven't been able to isolate an exact pattern but issue doesn't appear random either, it will keep showing up for certain boards, and then go away, then show up on other boards. Another symptom we see is that when a board downloads the systems successfully, during the final step of the process the JTAG TX LED on the board appears to turn solid green. On the boards that hang and fail, the same LED flashes rapidly while the process hangs. The monitor program logs show the following commands are run before the error appears: $ /home/$USER/DE10/monitorprogramtutorial/ $ make clean # The board name in quotes below is variable and appears to be unique to each board or connection $ /opt/intelFPGA_lite/18.1/quartus/bin64/quartus_pgm -c "DE-SoC [1-10]" --auto $ quartus_pgm -c "DE-SoC [1-10]" -m jtag -o "P;/opt/intelFPGA_lite/18.1/University_Program/Computer_Systems/DE10-Standard/DE10-Standard_Computer/verilog/DE10_Standard_Computer.sof@2" $ quartus_hps --cable="DE-SoC [1-10]" -o GDBSERVER --gdbport0=3212 --preloader=/opt/intelFPGA_lite/18.1/University_Program/Monitor_Program/arm_tools/u-boot-spl.de10-standard.srec --preloaderaddr=0xffff14f0 Running these commands manually results in the final command either: 1. Starting a GDB server very quickly: >>Resetting HPS. >>Downloading preloader....... >>Program loaded. PC set to program entry (0xFFFF0000) >>Setting vector base address register to: 0xffff0000 >>Running preloader.. >>Preloader successfully run. Starting GDB Server. Listening on port 3212 for connection from GDB 2. Hanging for a long time when 'Downloading preloader.......' and then failing at the 'Running preloader...................' stage and hanging indefinitely. Ending the process with Ctrl+C shows: Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: Fail to enable DEBUG feature Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: Failed to load program. Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Encounter JTAG AJI error while reading Control/Status Register Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 0 Error: Fail to READ ACCESS to the Physical Reg Error: Fail to write to MPU Module Reset Register Error: Engine failed to set down the hardware Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings Error: Peak virtual memory: 187 megabytes Error: Processing ended: Tue Aug 11 11:44:38 2026 Error: Elapsed time: 00:05:05 Error: Total CPU time (on all processors): 00:00:01 Any thoughts or suggestions are greatly appreciated.
AXI4-Lite Firewall IP core - Altera support request
Greetings Altera, Just FYI, I writing in the community forum, in addition to a sent an inquiry yesterday, through the website contacts form - https://www.altera.com/contact - in attempt to get into contact and start a conversation going with some of your FAEs regarding a problem our company and team is facing: Currently in one of our FPGA Designs utilizing Altera FPGAs (CycloneV SoC ARM (5CSEBA5)), there is a requirement to monitor and control data streams/transfers between AXI4 master and slave devices. We have to ensure those are occurring in the allowed (configurable) address ranges, and if not, such data transfer is canceled – both downstream and upstream, the master is kept aware, and an interrupt is driven out. A Nios II CPU shall be able to configure (access) this IP core – set these address ranges, read statuses, etc. Also it will be the recipient of the IRQ from core in case of faults. Basically, we are looking for a simple configurable (read&write) AXI4-Lite Firewall/Pass-through/Configurable Bridge (whatever you want to call it) type of IP core – that will sit between two AXI connected type devices (master on one-side & slave on the other) and oversee the communication between them. For Altera Cyclone V SoC FPGAs. At this point we cannot find such component from the Altera’s Quartus IP cores (Platform Designer) library. Also, it is not obvious for us how to, or, even if it is possible to ‘construct’ such device, from other IPs already available in the library ??? That’s why I am reaching to you for support on the matter. To check what approach or solution can you suggest , do you have anything available as service or ip core that could solve our problem, recommend us an IP vendor , etc... Here's a general block diagram of what we have in mind: (download the attached .png for better resolution) I hope we can talk soon. Best Regards, - Georgi M.
Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,
LVDS Output of FPGA
Hi all, I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects. There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently debugging an issue, and focused on enhancing the signal quality at the output of the FPGA. The output signal we measure in scope is not as good as we would expect. We expect a step signal, but the testing output shows a triangular signal! I have the following questions. 1) Is there settings/knobs I could tweak in my LVDS IP, or any other ideas to improve output signal quality? ( I learned about pre_emphasis setting), But other ideas could help. 2) Is there an inbuilt tool within FPGA to check the eye diagram or measure the output signal quality?instead of relying on an oscilloscope?. Note: I am using Quartus 2018 standard version. Let me know if you need further information. Thankyou.
Questa-ModelSim UI scaling problems in Linux
Hello Has anybody been able to solve the issue of UI of Questa not scaling correctly on linux with wayland? I am using Ubuntu 26.04 with wayland and UI is just tiny, icons, are so small i cannot read any text. When opening a new project, file explorer is also tiny. Fonts i could change in the config file but icons, menus and everything else is just extremely small. Problem is even worse on high resolution displays. Regards, Haris
Know-How: Licensing Guide
#sharing #debug #altera #alldevices #license Disclaimer: This article is provided as-is for educational purposes only, without warranty of any kind. Use the information at your own risk. Always verify implementations in your specific environment and consult official Altera documentation for production deployments. Introduction Licensing issues are one of the most common reasons FPGA tools fail to start. The good news is that most problems are configuration related and can be fixed quickly by following a simple, step-by-step approach. Sections 1: Start with the Error Message (Most Important!) Always look at the first licensing error message shown by the tool. This is usually the real issue. Any errors that appear later are usually caused by the first problem. Here’s are common error messages and what they usually mean: Invalid hostid → License does not match your machine ID Cannot find license file → Invalid or missing license path Unable to checkout a license → License not found, in use, or server issue 300: License version is outside the range of the contract → license file generated with blank FLEXlm error: Vendor daemon version is too old → daemon used mismatch or too old Cannot checkout uncounted license in Windows Terminal Services → Questa does not support remote desktop. Most common errors already have known fixes. Try searching the error message or key issue at: Altera Knowledge Base: https://community.altera.com/category/top/kb/knowledge-base Altera Community Forums: https://community.altera.com/category/forums For floating licenses, you can also check the FlexNet error code list: Error Code Descriptions Don’t try to fix everything at once. Fix the first error, then retry. In many cases, the rest will disappear automatically. 2: Check Your License (.dat) File Open the .dat license file using a text editor (for example, Notepad) and verify the following. i. Machine ID (NIC / HOST ID) The license is locked to a specific machine ID. Example in the license file: # Primary Machine ID-NIC ID 12AB34C56EF7 If the Host ID doesn’t match your machine ID, the license will not work. Helpful Tips 1: ----------------------------------------------------- START ----------------------------------------------------- Quartus software can automatically detect the Machine ID. To view this, go to Tools → License Setup, then check Local System Information and select one of the detected NIC IDs. ------------------------------------------------------ END ------------------------------------------------------ ii. License Type Licenses are set up differently, so confirm which type you have.Look for one of these lines: # Fixed Node License → Nodelocked license # Floating Server License → Floating license Nodelocked: Locked to one machine Floating: Served from a license server and shared Make sure you’re following the setup steps that match your license type. iii. Product License Summary Find the Product License Summary section and confirm it lists the tools/IP you’re planning to use. Examples: Quartus® Prime Software (Standard / Pro) Questa® FPGA Starter Edition (SWQUESTA) If a tool or IP is not listed here, it won’t be able to check out a license—even if the license file setup successfully. iv. License Expiration & Maintenance Licenses can look similar but behave very differently. We have: a. Perpetual License Has a Maintenance Expiration date You can use tool versions released before that date Example shown in license file: # Maintenance Expiration of 2026.06 # No license expiration date b. NonPerpetualLicense Has a hard expiration date License stops working after this date Example shown in license file: # License Expires 20Jun2026 Always doublecheck the license expiration & maintenance date before moving on. 3. Verify Environment Variables The tools use environment variables to find the license. If these are wrong, the tools may not find your license—or may use an old license file. Common environment variables: Different tools use different environment variables to locate the license. LM_LICENSE_FILE → Quartus® Prime SALT_LICENSE_SERVER → Questa* FPGA Edition Depending on the license type, they should point to: Nodelocked license: Full path to the .dat file Floating license: port@hostname Examples: LM_LICENSE_FILE=C:\licenses\license.dat LM_LICENSE_FILE=25000@licenseserver Next verify the environment variable. Open Command Prompt and run: echo %LM_LICENSE_FILE% If nothing is printed, the environment variable is either not set or the changes have not taken effect. If it is the latter, close and reopen the command prompt after making the changes. If the variable points to an incorrect location, update it accordingly. Note that outdated or incorrect environment variables are a very common source of issues. Helpful Tips 2: ----------------------------------------------------- START ----------------------------------------------------- There is a quick way to set using command line. Open Command Prompt and run: Windows: setx LM_LICENSE_FILE <path_to_license_file> Linux: setenv LM_LICENSE_FILE "<path_to_license_file>" ------------------------------------------------------ END ------------------------------------------------------ 4. Check the License Server (Floating Licenses Only) If you’re using a floating license, verify the server. On the client machine: Server hostname resolves correctly Network is working Firewall is not blocking the license port On the license server: License server process is running Vendor daemon is running Server log shows no fatal errors Licenses are available (not all checked out) If the server isn’t running properly, clients won’t be able to get licenses. 5. Scenario / Walkthrough i) Floating License Setup Walkthrough A floating license setup walkthrough (Know-How: Set Up a Floating License) is available to guide you through the complete process of configuring a floating license. Know-How: Set Up a Floating License (Step-by‑Step Walkthrough) | Altera Community - 352000 ii) Manual License File Download (License Email Not Received) If you generate a license but do not receive the license email within 5 minutes, you can manually download the license file using the steps below: Log in to SSLC. Navigate to Computers and License Files. Click the Primary Computer ID. Go to the ENTITLEMENTS tab. Select the relevant license (for example, LR‑****). Click the license file link to download the license file. Example shown below: iii) SSLC Access Denied Error Resolution If you encounter the message below when attempting to sign in to SSLC, please refer to the community thread linked below for the solution: Message:“You do not currently have access to this site. Please follow the instructions on the help page to request access.” Self service license server doesn't work | Altera Community - 352404 iv) Changing License Type (Fixed ↔ Floating) To change an existing license type: Log in to SSLC. Navigate to Computers and License Files. Navigate to the license file and click Edit in the drop-down menu. Change the License Type to FIXED or FLOAT, click Save. Now you can generate the license file with the Existing Computer. For your reference, this error occurs when you attempt to create a computer with the same NIC ID. You cannot create two computers with the same NIC ID, even with different license types. *Additionally, changing the license type will use up one rehost count. If all 3 rehost count have been used up, you can not change the license type for the specific computer anymore. Conclusion Licensing issues are almost always setup or configuration problems. Following this guide step-by-step starting with the error message will resolve most issues. If you’re still stuck after trying all the steps, feel free to post your issue on the Altera Community Forum (https://community.altera.com/category/forums) for help. When posting, please try to include the following: i. Error Details The exact licensing error message, copied as is If there are multiple errors, include the first one shown ii. Tool Information Product name (example: Quartus/Questa) Tool version (example: Quartus Pro 25.3/ Questa Altera FPGA Edition 2025.2) Operating system (Windows or Linux, version if known) iii. License Information License type: Nodelocked (fixed)/ Floating (network) Purchased / Evaluation license If possible, a copy of the license file (.dat) iv. What You’ve Already Tried Steps you have already checked or attempted Any workaround that partially worked The more complete your post, the faster the community (and Altera support staff) can help. Additional Altera Support Webpages For further information related to licensing, you may check out Altera Licensing Webpages for the wholesome experiences to get your FPGA licensing product setup and running with minimal hassle: FPGA Licensing Support Center Quartus® Prime Software Licensing Questions and Answers Additionally, we have FPGA Software Download and Installation Support webpage: FPGA Software Download and Installation Support Self Service Licensing Center (SSLC) Issues For issue related to the SSLC, please contact Customer Service if you encounter any of the following: Can’t find a product in SSLC Errors when generating a license file Errors when renewing a license file Unable to generate a companion or temporary license Unable to update license users or delegate administrators Need to transfer license ownership between accounts Contact Altera Customer Service here: https://licensing.altera.com/sslc/s/contact-customer-service For account login issue, please mail to: [email protected] License Purchase Inquiries For purchasing licenses, pricing questions, or commercial inquiries, please contact an Altera Authorized Distributor: https://www.altera.com/contact
SOLVED: BSP Editor NullPointerException on Debian 13 Linux
SOLVED: BSP Editor "New BSP" menu command is grayed out, so can't make any new BSP's, and opening any existing one from another computer throws: SEVERE: Available BSP type values for the --type argument are: [] SEVERE: BSP type "hal2" unknown. SEVERE: NullPointerException Based on other forum posts with a similar error, it seems like this is because the BSP Editor couldn't locate some of its own files. That seems likely here too since this is the first time it's used on this computer. But there's no problematic install path etc since I used the default. THERE ARE NO SPACES IN THE INSTALL PATH NOR THE PROJECT PATH. Everything else is working already for the Max 10: I can generate with Platform Designer, synthesize with Quartus, program SRAM with SignalTap, debug Nios V with RiscFree. Details are: Quartus Prime Lite 25.1std.0 Build 1129 10/21/2025 SC Lite Patches: None OS: Debian 13. This is what Ubuntu is based on, so it's very similar. And like I said everything else already works. USB came online already, not too hard. All it took was the Altera udev rules file 92 as usual, and the correct LD_LIBRARY_PATH so jtagd could find its own shared libs. Installed quartus into regular user account, not whole system, not as root. This is offered as an option in the installer if I recall correctly. Install path is the installer's default: /home/myuser/altera_lite/25.1std The project files are irrelevant here, since BSP Editor is already off-track as soon as it launches. "New BSP" is grayed out. SOLVED: BSP Editor is unable to find its own files without Altera's environment vars, which are provided when running inside niosv-shell. That's nonsensical to me, since any brain-dead program off the street can detect where its own binary loaded from, on any OS, and walk up the path from there to find the rest of its files, as a default if no env vars were provided. That's the first line of every binary or Tcl script I've ever written. Quartus main GUI seems to do it exactly that way. Anyone else struggling with this inexplicable rough edge should make sure your desktop's launcher icon invokes niosv-shell first, like this: altera_lite/25.1std/niosv/bin/niosv-shell --run altera_lite/25.1std/niosv/bin/niosv-bsp-editor To Altera: if you're struggling to maintain or improve your software because it relies on Tcl, contact me through my forum account. I could clean up a whole mess of rough edges like this one, and some other much-needed improvements.
