NIOS V: Systick based timeouts not available when using internal timer
Hello, We are using Quartus 25.1 Standard. I came across something, which I would consider a but in the BSP generated HAL files, or at least a major limitation in the usage of NIOS V. System Setup: NIOS V + JTAG UART NIOS V in internal Timer as Sys_clk_timer BSP Setting: Problems: The JTAG UART drivers have a timeout functionality based on the systick interrupt to avoid getting stuck, in case there is not JTAG UART connected, so the internal buffer fills up. --> see altera_avalon_jtag_uart_timeout() This used to work fine with: NIOS II Setup (using external Timer) NIOS V Setup with external Timer block as sys_clk_timer But when using the NIOS V internal as sys_clk_timer the JTAG UART timeout does not trigger and when calling alt_printf it gets stuck in altera_avalon_jtag_uart_write /* * No OS present: Always wait for data to be removed from buffer. Once * the interrupt routine has removed some data then we will be able to * insert some more. */ while (out == sp->tx_out && sp->host_inactive < sp->timeout) Analysis When I check the initialization routine of the JTAG UART altera_avalon_jtag_uart_init by stepping through with the debugger, I realize, the alarm is not setup: /* * No OS present: Always wait for data to be removed from buffer. Once * the interrupt routine has removed some data then we will be able to * insert some more. */ while (out == sp->tx_out && sp->host_inactive < sp->timeout) This is because the alt_ticks_per_second() returns 0 During the main() function alt_ticks_per_second() is correctly set to 10 (which is my setting from the BSP) The root cause, is the initialization order in alt_sys_init() within the generated alt_sys_init.c file: void alt_sys_init( void ) { ALTERA_AVALON_TIMER_INIT ( NIOS_SUBSYSTEM_TIMER_0, nios_subsystem_timer_0); ALTERA_AVALON_JTAG_UART_INIT ( NIOS_SUBSYSTEM_JTAG_UART_0, nios_subsystem_jtag_uart_0); ALTERA_AVALON_SPI_INIT ( NSC3_SUBSYSTEM_0_ADC_SPI, nsc3_subsystem_0_adc_spi); ALTERA_AVALON_SYSID_QSYS_INIT ( NIOS_SUBSYSTEM_SYSID_NIOS, nios_subsystem_sysid_nios); ALTERA_AVALON_UART_INIT ( NIOS_SUBSYSTEM_UART_IP, nios_subsystem_uart_ip); INTEL_NIOSV_M_INIT ( NIOS_SUBSYSTEM_INTEL_NIOSV_M_0, nios_subsystem_intel_niosv_m_0); } _alt_tick_rate is initalized to 0 per default and gets set duing alt_sysclk_init(), called from the INTEL_NIOSV_M_INIT Macro As seen above. The INTEL_NIOSV_M_INIT Macro is called last within alt_sys_init. Hence all other modules do see _alt_tick_rate = 0. Hence assume there is no sys tick timer present. Hence all sys tick based alarms are disabled. NOTE: The ALTERA_AVALON_TIMER_INIT Macro is called first. Which appears to be correct IMHO, so the Timer module works as sys tick timer @ Altera: Please advise on this issue. Is there any possibility to change the alt_sys_init initialization order? best regards Fabian
Using Quartus with softHSM
Hi, I am trying to use quartus to create a signed AES key that is created with softHSM: This command runs fine: $quartus_encrypt --family=agilex7 --operation=MAKE_AES_KEY -a test_aes_key.txt --module=softHSM --module_args='--token_label=MySoftHSM --user_pin=ignored --hsm_lib=/tmp/libSoftHSM' aes_key.qek --keyname=TestAESKey But when I follow the user guide to generate the efuse wrapped aes key, i got this error: $quartus_pfg --ccert -o ccert_type=EFUSE_WRAPPED_AES_KEY -o qek_file=aes_key.qek unsigned_efuse_aes_root0.ccert -o module=softHSM -o module_args="--token_label=MySoftHSM --user_pin=ignored --hsm_lib=/tmp/libSoftHSM" ... Error (21999): Found unsupported option string: module If I remove the module option, then i'd get this error code: Error (20351): Fail to execute function get_qek_root_key in file pgm_python_common_function Error (20353): Module: stratix10_encrypt.py, Function: check_qek, Line: 548 Error (20353): QEK Encrypted with HSM provided but module arguments are not specified Error (21589): Cannot retrieve encryption key from aes_key.qek. Make sure the encryption key file (*.qek) is valid and you enter the correct passphrase. Error (20398): Failed to create unsigned compact certificate file unsigned_efuse_aes_root0.ccert. Error: Quartus Prime Programming File Generator was unsuccessful. 5 errors, 0 warnings Any guidance on what to try next?Licensing ‘Know-How’ Guide
#sharing #debug #altera #alldevices #license Disclaimer: This article is provided as-is for educational purposes only, without warranty of any kind. Use the information at your own risk. Always verify implementations in your specific environment and consult official Altera documentation for production deployments. Introduction Licensing issues are one of the most common reasons FPGA tools fail to start. The good news is that most problems are configuration related and can be fixed quickly by following a simple, step-by-step approach. Sections 1: Start with the Error Message (Most Important!) Always look at the first licensing error message shown by the tool. This is usually the real issue. Any errors that appear later are usually caused by the first problem. Here’s are common error messages and what they usually mean: Invalid hostid → License does not match your machine ID Cannot find license file → Invalid or missing license path Unable to checkout a license → License not found, in use, or server issue 300: License version is outside the range of the contract → license file generated with blank FLEXlm error: Vendor daemon version is too old → daemon used mismatch or too old Cannot checkout uncounted license in Windows Terminal Services → Questa does not support remote desktop. Most common errors already have known fixes. Try searching the error message or key issue at: Altera Knowledge Base: https://community.altera.com/category/top/kb/knowledge-base Altera Community Forums: https://community.altera.com/category/forums For floating licenses, you can also check the FlexNet error code list: Error Code Descriptions Don’t try to fix everything at once. Fix the first error, then retry. In many cases, the rest will disappear automatically. 2: Check Your License (.dat) File Open the .dat license file using a text editor (for example, Notepad) and verify the following. i. Machine ID (NIC / HOST ID) The license is locked to a specific machine ID. Example in the license file: # Primary Machine ID-NIC ID 12AB34C56EF7 If the Host ID doesn’t match your machine ID, the license will not work. Helpful Tips 1: ----------------------------------------------------- START ----------------------------------------------------- Quartus software can automatically detect the Machine ID. To view this, go to Tools → License Setup, then check Local System Information and select one of the detected NIC IDs. ------------------------------------------------------ END ------------------------------------------------------ ii. License Type Licenses are set up differently, so confirm which type you have.Look for one of these lines: # Fixed Node License → Nodelocked license # Floating Server License → Floating license Nodelocked: Locked to one machine Floating: Served from a license server and shared Make sure you’re following the setup steps that match your license type. iii. Product License Summary Find the Product License Summary section and confirm it lists the tools/IP you’re planning to use. Examples: Quartus® Prime Software (Standard / Pro) Questa® FPGA Starter Edition (SWQUESTA) If a tool or IP is not listed here, it won’t be able to check out a license—even if the license file setup successfully. iv. License Expiration & Maintenance Licenses can look similar but behave very differently. We have: a. Perpetual License Has a Maintenance Expiration date You can use tool versions released before that date Example shown in license file: # Maintenance Expiration of 2026.06 # No license expiration date b. NonPerpetualLicense Has a hard expiration date License stops working after this date Example shown in license file: # License Expires 20Jun2026 Always doublecheck the license expiration & maintenance date before moving on. 3. Verify Environment Variables The tools use environment variables to find the license. If these are wrong, the tools may not find your license—or may use an old license file. Common environment variables: Different tools use different environment variables to locate the license. LM_LICENSE_FILE → Quartus® Prime SALT_LICENSE_SERVER → Questa* FPGA Edition Depending on the license type, they should point to: Nodelocked license: Full path to the .dat file Floating license: port@hostname Examples: LM_LICENSE_FILE=C:\licenses\license.dat LM_LICENSE_FILE=25000@licenseserver Next verify the environment variable. Open Command Prompt and run: echo %LM_LICENSE_FILE% If nothing is printed, the environment variable is either not set or the changes have not taken effect. If it is the latter, close and reopen the command prompt after making the changes. If the variable points to an incorrect location, update it accordingly. Note that outdated or incorrect environment variables are a very common source of issues. Helpful Tips 2: ----------------------------------------------------- START ----------------------------------------------------- There is a quick way to set using command line. Open Command Prompt and run: Windows: setx LM_LICENSE_FILE <path_to_license_file> Linux: setenv LM_LICENSE_FILE "<path_to_license_file>" ------------------------------------------------------ END ------------------------------------------------------ 4. Check the License Server (Floating Licenses Only) If you’re using a floating license, verify the server. On the client machine: Server hostname resolves correctly Network is working Firewall is not blocking the license port On the license server: License server process is running Vendor daemon is running Server log shows no fatal errors Licenses are available (not all checked out) If the server isn’t running properly, clients won’t be able to get licenses. 5. Scenario / Walkthrough i) A floating license setup walkthrough (Know-How: Set Up a Floating License) is available to guide you through the complete process of configuring a floating license. Know-How: Set Up a Floating License (Step-by‑Step Walkthrough) | Altera Community - 352000 ii) If you generate a license but do not receive the license email within 5 minutes, you can manually download the license file using the steps below: Log in to SSLC. Navigate to Computers and License Files. Click the Primary Computer ID. Go to the ENTITLEMENTS tab. Select the relevant license (for example, LR‑****). Click the license file link to download the license file. Example shown below: iii) If you encounter the message below when attempting to sign in to SSLC, please refer to the community thread linked below for the solution: Message:“You do not currently have access to this site. Please follow the instructions on the help page to request access.” Self service license server doesn't work | Altera Community - 352404 Conclusion Licensing issues are almost always setup or configuration problems. Following this guide step-by-step starting with the error message will resolve most issues. If you’re still stuck after trying all the steps, feel free to post your issue on the Altera Community Forum (https://community.altera.com/category/forums) for help. When posting, please try to include the following: i. Error Details The exact licensing error message, copied as is If there are multiple errors, include the first one shown ii. Tool Information Product name (example: Quartus/Questa) Tool version (example: Quartus Pro 25.3/ Questa Altera FPGA Edition 2025.2) Operating system (Windows or Linux, version if known) iii. License Information License type: Nodelocked (fixed)/ Floating (network) Purchased / Evaluation license If possible, a copy of the license file (.dat) iv. What You’ve Already Tried Steps you have already checked or attempted Any workaround that partially worked The more complete your post, the faster the community (and Altera support staff) can help. Additional Altera Support Webpages For further information related to licensing, you may check out Altera Licensing Webpages for the wholesome experiences to get your FPGA licensing product setup and running with minimal hassle: FPGA Licensing Support Center Quartus® Prime Software Licensing Questions and Answers Additionally, we have FPGA Software Download and Installation Support webpage: FPGA Software Download and Installation Support Self Service Licensing Center (SSLC) Issues For issue related to the SSLC, please contact Customer Service if you encounter any of the following: Can’t find a product in SSLC Errors when generating a license file Errors when renewing a license file Unable to generate a companion or temporary license Unable to update license users or delegate administrators Need to transfer license ownership between accounts Contact Altera Customer Service here: https://licensing.altera.com/sslc/s/contact-customer-service For account login issue, please mail to: loginsupport@altera.com License Purchase Inquiries For purchasing licenses, pricing questions, or commercial inquiries, please contact an Altera Authorized Distributor: https://www.altera.com/contact
Agilex 5 – Critical HSSI Error in JESD204B Example Design
Hi, I am bringing up the JESD204B interface on the dev kit. For this, I used the "Generate Example Design" option with the following parameters: When I generate the project and start synthesis, it reaches the "HSSI Support Logic Generation" stage, and Quartus reports the following critical error: It turns out that the generated file contains an inconsistency in the generated HSSI metadata. My fix was to replace the entry in: The problem is that after updating the Qsys file, it gets changed back to intel_jesd_RX, and HSSI reports the critical error again. If there is already a fix or workaround for this issue, please let me know. For now, I added a simple script that I run from PowerShell: that replaces this value with the correct one:
NIOS does not start after SW download (timing issue?)
Hi, Recently I got an old Arria V design to update. It is in Quartus II 15.0 containing the following main components (in Qsys design): NIOS II soft processor 2x UniPHY DDR3 RAM controller (soft version, not hard), 72 bit wide data running at 400MHz clock (800Mb/s) 2x Triple Speed Ethernet with 4x SGDMA The design uses only 40k ALMs out of 190k so it fits well but I have timing issues (slack) on pll_afi_clk for one or both DDR3 controllers. I can reduce it by a lot of fine tuning on synthesizer and fitter settings but when I change a bit in the design timing results go wrong and tuning has to be started again. Both FW and SW are downloaded to SRAM by ByteBlaster. I found when the slacks are big (>0.1ns) NIOS never starts after downloading the SW. When it is small or completely eliminated, NIOS starts in most of the cases (but not always). Is this normal for such a design, or am I doing something wrong? I have never seen such behaviour before. Can this timing issue affect the NIOS processor on such a way or should I search in another direction to solve the problem?
Nios V license
Hi, I need to apply Nios V free license, but in FPGA Self Service Licensing Center, I got error all the time, I signed in successfully, but it says "You do not currently have access to this site" always, as shown in the attached figure. Please help fix this issue, or is there other way to get the license? Thanks.
S10 hps fpga2sdram bridge low speed
Hello, i have some problems I have a project with stratix 10 with hps I need to use ddr4 with hps, so I enabled 3 fpga2sdram bridges with 128 bit width Via u-boot smc configured and enabled them, but measured speed is not enough. When I use onle one bridge my speed is approximately 32 gbit/s (bridge and master frequency 350 MHz) But when I use all 3 bridges it becomes 20 gbit/s I use avmm bridge to connect to axi fpga2sdram bridge with 128 bits width, max pending writes 16, max burst size 128, use only write to bridge ECC in emif (hmc) is disabled I tried to use QoS for bridges, set them to bypass P.S. If i use the same board with firmware without hps, i get 130 gbit/s (with disabled hps) Quartus Pro 21.4 Any help would be useful!
NiosV and juart-terminal
I had a project which works fine under niosII. I upgrade all the project with niosv and all seems fine except printing values in juart-terminal. Here is the main code : #include <stdio.h> #include "system.h" #include "altera_avalon_pio_regs.h" #include <altera_avalon_i2c.h> #include <unistd.h> #include <string.h> int main() { //* ALT_AVALON_I2C_DEV_t *i2c_dev; //pointer to instance structure alt_u8 txbuffer[20]; alt_u8 rxbuffer[20]; float co2Concentration = 0; float temperature = 0; float humidity = 0; alt_u32 co2U32 = 0; alt_u32 tempU32 = 0; alt_u32 humU32 = 0; ALT_AVALON_I2C_STATUS_CODE status; i2c_dev = alt_avalon_i2c_open("/dev/i2c"); //Ouverture du périphérique i2c et récupération d'un pointeur if (NULL==i2c_dev) { printf("Error: Cannot find /dev/i2c\n"); return 1; } //set the address of the device using alt_avalon_i2c_master_target_set(i2c_dev,0x61); //Définition de l'adresse du composant adressé 0x61 pour le SCD30 txbuffer[0]=0x00; txbuffer[1]=0x10; txbuffer[2]=0x00; txbuffer[3]=0x00; txbuffer[4]=0x81; //Remplissage du buffer pour configurer le SDC30 en Continous measurement status=alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 5,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant if (status!=ALT_AVALON_I2C_SUCCESS) return 1; //FAIL while(1) { txbuffer[0]=0x02; txbuffer[1]=0x02; //Remplissage du buffer pour déterminer si les données sont prêtes alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2,ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer au composant rxbuffer[1]=0x00; usleep(3000); // Il faut attendre au moins 3ms avant de demander la réponse alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 3,ALT_AVALON_I2C_NO_INTERRUPTS); //Récupération de la réponse du composant si rxbuffer[1]==0x01 alors les données sont prêtes if(rxbuffer[1]==0x01) { txbuffer[0]=0x03; txbuffer[1]=0x00; //Remplissage du buffer pour la lecture des données alt_avalon_i2c_master_tx(i2c_dev,txbuffer, 2, ALT_AVALON_I2C_NO_INTERRUPTS); //Envoi du buffer de lecture et récupération des données usleep(3000); //Wait 3ms before data available alt_avalon_i2c_master_rx(i2c_dev,rxbuffer, 18,ALT_AVALON_I2C_NO_INTERRUPTS); //Read datas co2U32 = (alt_u32)((((alt_u32)rxbuffer[0]) << 24) | (((alt_u32)rxbuffer[1]) << 16) | (((alt_u32)rxbuffer[3]) << 8) | ((alt_u32)rxbuffer[4])); tempU32 = (alt_u32)((((alt_u32)rxbuffer[6]) << 24) | (((alt_u32)rxbuffer[7]) << 16) | (((alt_u32)rxbuffer[9]) << 8) | ((alt_u32)rxbuffer[10])); humU32 = (alt_u32)((((alt_u32)rxbuffer[12]) << 24) | (((alt_u32)rxbuffer[13]) << 16) | (((alt_u32)rxbuffer[15]) << 8) | ((alt_u32)rxbuffer[16])); memcpy(&co2Concentration, &co2U32, sizeof(co2Concentration)); memcpy(&temperature, &tempU32, sizeof(temperature)); memcpy(&humidity, &humU32, sizeof(humidity)); } printf("---------------------------------------------------------\n"); printf("SCD30\n"); printf("Concentration de CO2 : %f ppm\n",co2Concentration); printf("Température : %.1f °C\n",temperature); printf("Humidité relative : %.1f %% \n",humidity); usleep(500000); } } I put a breakpoint just before the printf and the values are good : but when i print the values in the juart-terminal : I can't figure out why the printf does not work as i expect. Someone could help me to understand this problem ? Thanks Eric
