Recent Discussions
SDRAM NIOSV ash-riscv-gdb-server error
Hi, i did a simple sdram +niosv projet following DE10-Lite and sdram controller ip | Altera Community but wen i programed the de10-lite board and use the ashling vscode extension but when i try to launch the debug i obtain an error : ash-riscv-gdb-server: Ashling GDB Server for RISC-V (ash-riscv-gdb-server). ash-riscv-gdb-server: v25.2.1, 09-May-2025, (c)Ashling Microsystems Ltd 2024. ash-riscv-gdb-server: ash-riscv-gdb-server: Initializing connection ... =thread-group-added,id="i1" GNU gdb (GDB) 13.2 Copyright (C) 2023 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=x86_64-w64-mingw32 --target=riscv32-unknown-elf". Type "show configuration" for configuration details. For bug reporting instructions, please see: <https://www.gnu.org/software/gdb/bugs/>. Find the GDB manual and other documentation resources online at: <http://www.gnu.org/software/gdb/documentation/>. For help, type "help". Type "apropos word" to search for commands related to "word". Warning: Debuggee TargetArchitecture not detected, assuming x86_64. =cmd-param-changed,param="pagination",value="off" ash-riscv-gdb-server: Cannot set the JTAG frequency, continuing with auto adjust mode ash-riscv-gdb-server: Failed to get JTAG frequency from the debug probe ash-riscv-gdb-server: Connected to target device with IDCODE 0x31050dd using USB-Blaster-2 (1) via JTAG at 0.00MHz. ash-riscv-gdb-server: Info : Active Harts Detected : 1 ash-riscv-gdb-server: Info : Core[0] Hart[0] halted ash-riscv-gdb-server: Info : [0] System architecture : RV32 ash-riscv-gdb-server: Info : [0] Debug version : v1.00 ash-riscv-gdb-server: Info : [0] Number of hardware breakpoints available : 1 ash-riscv-gdb-server: Info : [0] Number of program buffers: 8 ash-riscv-gdb-server: Info : [0] Number of data registers: 2 ash-riscv-gdb-server: Info : [0] Memory access -> Program buffer ash-riscv-gdb-server: Info : [0] Memory access -> Abstract access memory ash-riscv-gdb-server: Info : [0] CSR & FP Register access -> Abstract commands ash-riscv-gdb-server: ash-riscv-gdb-server: Waiting for debugger connection on port 47595. ash-riscv-gdb-server: Press 'Q' to Quit. ash-riscv-gdb-server: Got a debugger connection from 127.0.0.1 on port 47595. Program received signal SIGINT, Interrupt. 0x04000004 in ?? ()
Address Space?
Hi I am confused about the address space requirements when using your own Avalon master in a custom module. (see attached) Why do I have to use more address bits than I need when I only drive one module. It appears that I have to add 2 extra bits to my address space for every module I go through to account for the interconnection fabric. This means that the address I generate has to be 28 bits instead of the 24 bits I need to address the RAM I know it is probably something stupid I am doing here. What am I missing? Thanks for the help
NIOSV firmware stuck when juart-terminal is not open for the print messasges.
Hi, I am facing an issue where the NIOSV firmware gets stuck if the JUART terminal is not open for printing messages. Once I open the JUART terminal, everything works fine. Is there any way or BSP setting I can use to prevent the NIOSV firmware from getting stuck when the JUART terminal is not open?How to reduce ROM/RAM requirements for a NIOSV Compact CPU Platform?
Hello ALTERA NIOSV Experts, I am trying to create a system in Quartus Platform Designer which has the following components: A 1G Tri mode ethernet IP (with 32 bit AVALON-ST TX/RX interfaces using minimum sized FIFOs) A RS 232 UART with no FIFO A couple of small FIFOs using AVALON-ST interfaces for data in and out of Platform via Conduits A NIOSV Compact CPU A JTAG UART ROM for NIOSV RAM for NIOSV My questions are about how to reduce the ROM (for the NIOSV compacts program) and RAM to the minimum amount. I am trying to shoehorn this all into a MAX10 FPGA ( Altera Max 10 part number 10M08SAU169I7G). When i build the BSP for this platform, with a "Hello World" program, it seems to need around 128 Bytes of ROM and several KBytes of RAM. Why is the program so large ? I expect it has to do with the BSP adding in drivers for all the Platform IP and it is getting bloated. What tactics are available for me to use in the Ashling RISC FREE IDE which i am using to create my BSP and/or Platform Designer to reduce the program size ? The FPGA i am trying to use only has around 48 K Bytes of RAM available in total ...so maybe this is not possible and i need a bigger FPGA of course ! Thanks for your help, Dr Barry
Nios V Hardware Interrupt Limitations
Hello, Based on the Nios V Processor Reference Manual and AN 978 Nios V Processor Migration Guidelines, Nios V supports only 16 hardware interrupts, whereas Nios II supports 32. Additionally, the External Interrupt Controller is not available in Nios V. Since Nios II has been deprecated, we are evaluating the transition to Nios V. However, our system requires more than 16 hardware interrupts. Does Intel provide any recommended approach for handling more than 16 hardware interrupts in Nios V? Are there plans to extend this capability in future releases? Best regards.Unable to Download top.par from Stratix 10 SDM Bootloader Design Example
Hello, I am trying to download the top.par file from the following Intel design example page: Stratix 10 FPGA SDM Bootloader for the Nios® V/G Processor Stratix® 10 FPGA – SDM Bootloader for the Nios® V/g Processor Design Example When I click on “Download top.par”, I consistently receive the following error: "The requested URL was rejected. Please consult with your administrator. Your support ID is: 4878817614298363410" This happens across different browsers and systems, and I am logged into my Intel/Altera account when accessing the page. Could you please advise: Whether this is a known issue with the download link If there are any access or permission requirements Or if there is an alternative way to obtain the top.par file Any guidance or a corrected download link would be greatly appreciated. Thank you for your support.
Brand new Bittware S5-PCIe-HQ not working with Quartus 13.1 CentOS 6.5
Hi, We have started working with this FPGA on CentOS 6.5, we managed to get the board recognized by Linux and we can even use the Bittworks Toolkit to read sensors and communicate with the board. The problem is after installing Quartus, because it doesn’t list any Stratix devices when creating a new project and we haven’t been able to create any VHDL code to program it. We are using Quartus 13.1 Subscription Edition and we have a license file. The board is currently connected with a micro-USB to USB cable because when is brand new, the manual says it won’t be detected on the PCIe connector. Is there any special requirement to get Quartus to recognize this board? Regards, PaulError creating Nios II Application and BSP from Template
I got this error while trying to create a Nios II Application and BSP from Template from a .sopcinfo file. Any hints? Thank you ! Executing: ./create-this-bsp --cpu-name nios2_cpu --no-make (F:\fsoc_lab\software\d_bsp) 2 [main] bash (7548) C:\intelfpga_lite\18.1\quartus\bin64\cygwin\bin\bash.exe: *** fatal error - cygheap base mismatch detected - 0xECD408/0x10ED408. This problem is probably due to using incompatible versions of the cygwin DLL. Search for cygwin1.dll using the Windows Start->Find/Search facility and delete all but the most recent version. The most recent version *should* reside in x:\cygwin\bin, where 'x' is the drive on which you have installed the cygwin distribution. Rebooting is also suggested if you are unable to find another cygwin DLL.
How to use SDRAM IP core on Agilex 3?
I am testing my project on Atum Nios V starter kit from terasic, which bases on Agilex 3 (A3CZ135BB18AE7S) and SDRAM(IS42VM32160G-6BLI). my purpose is, realize a Nios V system with RTOS and use the SDRAM as the program ram of the RTOS. My question: Agilex 3 is supported only by the higher version such as quartus pro 25.3, and the SDRAM ip is supported by previous old version quartus. do you have any solution that i can reuse the avalon interface SDRAM IP core on Agilex 3? thanks.