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Run-time errors using EMIF in Agilex 5 NIOS-V design
Hello, I am using Quartus Prime Pro 26.1.1, with the Agilex 5 development board (AXE5-Eagle). I am trying to run the NIOS-V code from the LPDDR4 memory, using JTAG to download/debug. The reset and exception vectors are set to the On-Chip RAM. I used the sample design provided for that board - AXE5 Eagle mipi_hdmi_mira220 and removed everything related to MIPI and HDMI. Added JTAG Uart IP. The resulting sample design is attached (mipi_hdmi_mira220.zip). In the software/ directory you can also see the FreeRTOS BSP I used. I created a simple FreeRTOS application that just prints some string to stdout. What I am seeing is - the RISC-V processor throws exceptions - one of the following - Misaligned Read Address, Misaligned Write Address or Invalid Instruction. This happens in alt_load_section(). If I execute step-by-step, no exception is thrown. But if I just run the application it fails. Is there something else that need to be added/updated/changed, in order to be able and execute code from LPDDR4 using the EMIF IP? I could not find any existing sample design, using NIOS-V and EMIF, with code execution from EMIF. Thank you, D.
Nios V/g load-writeback hazard
Summary On a NiosV/g core, a long-latency load from an on-chip memory immediately followed by a short-latency load from the core's own TCM returns the TCM load's data in both destination registers. The first load's writeback is lost. lw a0, 0(t0) # t0 -> On-chip memory lw a1, 0(t1) # t1 -> DTCM (core-local) # a0 and a1 both end up holding the DTCM value Inserting a single instruction between the two loads is enough to avoid it. Two on-chip memory loads back to back are fine, and so is the reverse order (TCM load first, then the on-chip memory load). Minimal reproducer Assembly: _start: lui t0, 0x40 # t0 = 0x00040000 on-chip memory ("input memory") lui t1, 0x10 # t1 = 0x00010000 DTCM (core-local) lui t2, 0xe0 # t2 = 0x000e0000 2nd on-chip memory ("output memory") li a2, 0x47414c47 # a value distinct from the DTCM sentinel sw a2, 0(t0) # ...store it into input_mem nop # let the store retire. The hazard is about two nop # adjacent *loads*; keep everything else well nop # clear of the pair below so the test stays nop # unambiguous. lw a0, 0(t0) # long-latency load: on-chip memory (input memory) lw a1, 0(t1) # short-latency load: DTCM, immediately after sw a0, 0(t2) # output_memory[0] = result of the AXI load sw a1, 4(t2) # output_memory[1] = result of the DTCM load spin: j spin System details NiosV/g data_manager (AXI master) is directly connected to on-chip memories and pipeline stages are limited to 3 in Platform Designer.
Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,
Dual Port Nios V BSP error
I've created a Nios V qsys with dual port onchip memory in Quartus Pro 26.1 True dual port, first port connected to instruction manager, second - to data manager. Base addresses automatically assigned the same to both. But i'am unable to create the BSP due to memory regions overlapping error! Of course the addresses are same - its the same physical onchip memory! Any solytion, please? Regards, Vlad.
set_output_delay explained for dummies
Hello. I have tried to wrap my brain around the documentation describing "set_output_delay", but I just don't seem to get it. My brain thinks like this: "Relative to the rising-edge of my output clock, the output data needs to be valid after 1 ns and remain valid for 2 ns". The documentation describes this: "The maximum output delay (-max) is used for clock setup checks or recovery checks and the minimum output delay (-min) is used for clock hold checks or removal checks. " So to me (please correct me if I'm wrong), "setup" sounds like the earliest time the data needs to be valid, and "hold" sounds like where the data is no longer required to be valid....But datasheets usually define setup as the time to the left of the clock, and hold as the time to the right of the clock. Since the valid window is to the right, one of these values should be negative? set_output_delay -max -1 set_output_delay -min 3 am I even close?[Test only]How to verify Agilex 3 in radiation tolerant environment
We're running an Agilex 3 design in a radiation-tolerant application and I'm trying to decide between two error-handling strategies: (1) just log all SEU events and let the system keep running, or (2) trigger an immediate reconfiguration or system reset on any SEU. The LSM handles single-bit and double adjacent bit errors via ECC, so my concern is specifically around what happens when we get a multi-bit error beyond ECC correction capability — what does the hardware actually do at that point, and why does that distinction matter for choosing between these two strategies?
gdb server problem when debugging
Hello, I'm running Quartus12.0sp2 on a windows 11 computer and I want to use the nios 2 eclipse tools to build, run and debug. Building and running works, but I encounter a problem with debugging via usb blaster. I get the error message 'Error starting gdbserver - see console for details'. If I start nios2-gdb-server.exe manually, I get the error message that two .dll files are missing: 'jtag_client.dll' and 'cygwin1.dll'. Both are present in some subfolders of c:/altera/12.0sp2. This behaviour does not change when I start eclipse or gdbserver from the NiosII command shell. Funnily, there is also a file 'nios2-gdb-server-fs2.exe' in the installation path, which seems to run. I tried tricking, by renaming this file into 'nios2-gdb-server.exe'. If I do so, the error message disappears, but the debugging process stops when trying to download the .elf file, at the step 'Launching: Stop processor if running'. I found an old discussion about a similar problem in the forum: Win7-Problem with NIOS-II debugger, can't start gdbserver | Altera Community - 224719 but there's also no clear solution for me. Has anyone else encountered a similar problem? Or can anyone explain what's the difference between 'nios2-gdb-server.exe' and 'nios2-gdb-server-fs2.exe'? Or does know where I have to change a Path such that gdb-server can find the .dll files? I'm quite lost and would appreciate any help. Thanks, TimoNios IDE CPU Detection
Hi, I am trying to create bsp and software for Nios V , using Eclipse IDE. When specifying a new projcet and its .sopc file i see message CPU not detected. And i also see message the NIOS_EDS environment variable not set. See screen shot attached . I verified via command prompt the environment variable is set and can be verified. Also i noticed there are no examples installed at this path : C:\intelFPGA_lite\24.1std\nios2eds Looking forward to resolve these issues, Thanks, Regards,Need a way to make firmware upgrade
Hello, I'm using altera cyclone with flash and Sram and usb_uart. My goal is to upgrade the commands to the nios processor(upgrade the Nios code) without using jtag. I want the cpu to read its commands from the flash device and If I want to change the commands I will simply write them to the flash using a elf file that will written by the PC to the Flash. after the write, I'll reset the system and the processor would run with the new commands. Is there a way to do that? If so, I would love to get all of the commands that do that. Thanks. asaf