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NIOS2 filesystem support
We have a system running on NIOS 2 processor with Cyclone5 FPGA and ecos RTOS. We are planning to remove the OS dependency and convert the application to baremetal. Already JFFS filesystem and FIS filesystem are being used in the application. Is there any filesystem libraries that can be used in baremetal? Files are having read and write access. Any specifc links to some examples of the usage of the same in NIOS 2 processor?NIOS does not start after SW download (timing issue?)
Hi, Recently I got an old Arria V design to update. It is in Quartus II 15.0 containing the following main components (in Qsys design): NIOS II soft processor 2x UniPHY DDR3 RAM controller (soft version, not hard), 72 bit wide data running at 400MHz clock (800Mb/s) 2x Triple Speed Ethernet with 4x SGDMA The design uses only 40k ALMs out of 190k so it fits well but I have timing issues (slack) on pll_afi_clk for one or both DDR3 controllers. I can reduce it by a lot of fine tuning on synthesizer and fitter settings but when I change a bit in the design timing results go wrong and tuning has to be started again. Both FW and SW are downloaded to SRAM by ByteBlaster. I found when the slacks are big (>0.1ns) NIOS never starts after downloading the SW. When it is small or completely eliminated, NIOS starts in most of the cases (but not always). Is this normal for such a design, or am I doing something wrong? I have never seen such behaviour before. Can this timing issue affect the NIOS processor on such a way or should I search in another direction to solve the problem?
Error creating Nios II Application and BSP from Template
I got this error while trying to create a Nios II Application and BSP from Template from a .sopcinfo file. Any hints? Thank you ! Executing: ./create-this-bsp --cpu-name nios2_cpu --no-make (F:\fsoc_lab\software\d_bsp) 2 [main] bash (7548) C:\intelfpga_lite\18.1\quartus\bin64\cygwin\bin\bash.exe: *** fatal error - cygheap base mismatch detected - 0xECD408/0x10ED408. This problem is probably due to using incompatible versions of the cygwin DLL. Search for cygwin1.dll using the Windows Start->Find/Search facility and delete all but the most recent version. The most recent version *should* reside in x:\cygwin\bin, where 'x' is the drive on which you have installed the cygwin distribution. Rebooting is also suggested if you are unable to find another cygwin DLL.eCoS OS throws execption when freeing memory
We have a firmware applicaiton that makes use of eCoS RtoS and NIOSII core. We have a logic that we first allocate memory dynamically and then if required delete the previous allocated memory and allocate bigger one - this step goes on until requirement is met. But we are observing exception from eCos during execution of these steps - in other words say when we ietrate over the above logic for 7th time, while freeing memory that time we get exception but allocation which is done prior to free succeeds: ExceptionHandler(data = 0x0, exception_number = 0x0, info = 0x017FFF74) cyg_hal_exception_handler(regs = ???) _software_exception_handler(asm) exception Cyg_Mempool_dlmalloc_Implementation::free(this = 0x0158AD40, mem = ???, unnamed = ???) Cyg_Mempolt2<Cyg_Mempool_dlmalloc_Implementation>::free(this = 0x0158AD40, p = ???, size = ???) free(ptr = ???) npfree(ptr = 0x017136A0) vf_free_buffer(buffer = 0x017136A0, size = 0x0007E000) vfwrite_locked(buf = 0x016956B0, size = 0x1, items = 0x0400, vfd = 0x01696F10) vfwrite(buf = 0x016956B0, size = 0x1, items = 0x0400, vfd = 0x01696F10) getfile(asm) WriteFileToFlash(notUsed = 0x0) ecos_thread_entry(entry = 0x0D) Cyg_Scheduler_Base::get_current_thread(inline) Cyg_Thread::self(inline) Cyg_Thread::exit(inline) Cyg_HardwareThread::thread_entry(thread = 0x01262448) end of frame Can anyone please let me know why exception is thrown at later part of step process execution and what the fix for this issue?
Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,
DK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails
Hello, I am using the following board and host environment: Board: Agilex 7 FPGA I-Series Development Kit, DK-DEV-AGI027-RA Serial number: 8100604 Quartus Prime Pro: 25.3.1 Host OS: Windows 11 Pro Before this issue, the board was working normally with CXL ED and PCIe designs. Issue summary After successfully running a modified version of the "Nios V Hello" tutorial design (SOF + ELF) on this kit, Quartus Programmer can no longer detect the JTAG chain reliably. "Auto Detect" fails, and the JTAG Chain Debugger reports unknown devices and possible JTAG signal issues. Steps and observations 1. I modified the Nios V Hello tutorial design (SOF + ELF), including pin assignments and power management & SmartVID assignments, to match DK-DEV-AGI027-RA. Programming completed successfully, and I confirmed the expected "Hello" output. After that first run, I attempted to download an updated SOF, but Quartus Programmer "Auto Detect" failed. JTAG Chain Debugger screenshot: Programmer/Debugger log: !Error: JTAG chain problem detected !Error: TDI connection to the first detected device UNKNOWN_00000001 might be shorted to GND !Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_00000001 might have a problem !Info: Detected 2 device(s) !Info: Device 1: UNKNOWN_00000001 !Info: Device 2: UNKNOWN_020D10DD Recovery attempts and results 2. Connected an external USB-Blaster II to J10, set SW8.3 = ON, and completed MAX10 recovery successfully. 3. Set SW8.3 = OFF to attempt FPGA recovery. Quartus Programmer Auto Detect still failed. 4. Loaded the predefined fpga_recovery.cdf and attempted to program AVSTX8.pof, but it failed with: Error(209062): Flash Loader IP not loaded on device 2 Error(209012): Operation failed 5. Set SW8.2 = ON to remove the FPGA from the JTAG chain, then successfully programmed AVSTX8.pof into QSPI. 6. Set SW8.2 = OFF again, but Auto Detect still failed. 7. Removed the external USB-Blaster II and tried the embedded JTAG interface. Auto Detect still failed. Questions. Are there additional recommended steps beyond MAX10 recovery and programming the recovery POF to QSPI (for example, specific switch combinations, a required full power-cycle sequence, or other board-level recovery steps)? If MAX10 recovery completes but JTAG remains broken on both external and embedded JTAG, does this suggest a likely hardware issue (JTAG path, FPGA, or related circuitry) that requires RMA? Is there anything in the Nios V Hello tutorial flow that could plausibly cause this condition (for example, power management settings, pin assignments, or JTAG-related settings)? If needed, I can share additional logs, exact switch settings, and any other diagnostics you recommend. Thanks.
No Nios II target connection
Hi, I'm trying to get the Hello World Nios II example to run on an Cyclone 10 GX. The design build and the sof-programming run without a problem. But the Nios II Eclipse can't find the Nios as target connection. In the "Run Configuration" dialog it shows: No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded. The Nios II system is pretty basic: with the following settings: Clk Input is 100 MHz (50 Mhz doesn't work neither) Reset Input is active high Nios II: Nios II/e Reset/Exception vector memory: OnChipRAM.s1 Include JTAG Debug The rest is unchanged OnChipRAM: Type: RAM Block type: Auto Size: 200000 bytes The rest is unchanged The other components (JtagUart / SystemID / PioOutput) have the default settings And I've checked, that the Nios Core is part of the design (using the Technology Map Viewer of the final snapshot). Can you please give me a hint what I'm doing wrong? Thanks