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Nios-V alt_epcq_controller_write() Problem
Hi, I have a flash on my custom board which is MT25QU01G. The flash is connected to Nios-V/g with Epcq Controller. I am trying to erase, write, read sectors from flash. Before write and erase I unlock all sectors and after write and erase I lock all sectors. The problem is that my alt_epcq_controller_write() returns success(0) however it doesn't write to flash memory. I read same data from same place and it is not changed. I also look that memory from memory browser and still nothing changed. I call erase method before each write method since it is nor flash but nothing happens. Could you please help me about the problem. Thanks, BalerionSolved124Views0likes13CommentsAhsling RiscFree IDE 25.1.1: Unresolved inclusion
Hello, I'm making Nios V test project for Agilex 5 (Arrow AXE5000 Devkit), following instructions in AN 985 Nios V Processor Tutorial. It works basically, I can download and run Nios application on the target. Source window is marking all include files as "unresolved" although the project compiles fine. I can manually add links to all missing includes (most from /bsp/inc folders, some from riscfree/toolchain/riscv32-unknown-elf) to the app tree to resolve the issue. But apparently there's something wrong with the import Cmake project flow. Am I missing a step in the instructions? Regards FrankSolved109Views0likes4Comments
Created Free NIOSV IP evaluation license but did not get any license file by email?
Hi ALTERA NIOSV experts, I have created licenses (the free evaluation type) through the Intel Altera Licensing portal for NIOSV-c, NIOSV-g, and NIOSV-m IP types. I get 3 messages saying a license has been created and i can see all the correct fields are filled in on the license form each time. It then says you will get a license by email. But after 2 hours i still have not received anything from Intel-Altera. Is there a problem with this licensing platform ?Is there a time delay between creating a license and actually getting it by email ? Usually this occurs very quickly, but not in this case ! Any suggestions or help much appreciated ! Thanks, Barry41Views0likes6CommentsERROR building simple NIOSV Compact project
Hello and greetings All Quartus + NIOSV experts, or indeed anybody who can help me fix this error ! I am trying to build a System Verilog design, based on Platform Designer, which uses a NIOSV compact IP core. I am using Quartus Prime Version 25,1 Standard Edition on a Windows 10 Machine. When trying to compile my test design i get these 2 errors : Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "niosv_cpp_fsm" at niosv_cpp_fsm.sv(18) due to previous errors Error 10112 is caused by previous error 10170. Does anybody have an idea why i get these errors ? I can't see the offending SV code because its encrypted (of course!). Is there a fix as well for this problem ? Thanks for any help, Dr Barry HSolved74Views0likes10Comments
No Nios II target connection
Hi, I'm trying to get the Hello World Nios II example to run on an Cyclone 10 GX. The design build and the sof-programming run without a problem. But the Nios II Eclipse can't find the Nios as target connection. In the "Run Configuration" dialog it shows: No Nios II target connection paths were located. Check connections and that a Nios II .sof is downloaded. The Nios II system is pretty basic: with the following settings: Clk Input is 100 MHz (50 Mhz doesn't work neither) Reset Input is active high Nios II: Nios II/e Reset/Exception vector memory: OnChipRAM.s1 Include JTAG Debug The rest is unchanged OnChipRAM: Type: RAM Block type: Auto Size: 200000 bytes The rest is unchanged The other components (JtagUart / SystemID / PioOutput) have the default settings And I've checked, that the Nios Core is part of the design (using the Technology Map Viewer of the final snapshot). Can you please give me a hint what I'm doing wrong? Thanks5KViews0likes9CommentsNios-V C++ Debug Problem
Hi all, I am trying to debug a simple nios-v C++ app but I am getting an error while debugging. The problem is when I create a project with the following commands niosv-bsp -c -p=niosv.qpf -s=niosv.qsys -t=hal software/bsp/settings.bsp niosv-app -b=software/bsp -a=software/app -s=software/app/hello.cpp it gives an error as "Launching app Default has encountered a problem. Error in services launch sequence GDB prompt not read." However, when I execute the following commands to create a project niosv-bsp -c -p=niosv.qpf -s=niosv.qsys -t=hal software/bsp/settings.bsp niosv-app -b=software/bsp -a=software/app -s=software/app/hello.c I can debug it without a problem. Could you please help me about how to debug a cpp application? Thanks, BalerionSolved870Views0likes13CommentsQuartus 25.x alternative to nios2-terminal
I'm using an Agilex 5 device and need to enable USB0(2.0) which requires HPS_IOA_1 through 12. I have been using HPS_IOA_3 and HPS_IOA_4 for the a Linux terminal over UART0 but I have to give this up in order to gain USB0(2.0) capability. ChatGPT said no problem - just use nios2-terminal which uses the JTAG connection. However, nios2-terminal doesn't seem to be included in any Quartus 25.x package anymore. What is a good alternative way to establish a Linux terminal session if UART0 is not available? Did "nios2-terminal" become something else in newer Quartus releases?Solved55Views0likes3Comments
Ashling RiscFree Nios V Error 2 and CMake Errors
Hello! I was building a Nios V/m systems to blink some LEDs. I am getting these errors I have followed the instructions from this forum post a few months ago: Ashling RiscV NiosV errors | Altera Community By setting the path variables I was able to get rid of some of the errors, but the ones pictured are still present. The program is able to run on the FPGA and does work correctly, so I think these errors might be a false error? I still would like to solve them. I am using Quartus V24.1-STD to generate the hardware, and Ashling RiscFree IDE V25.1.1, as well as the nios V shell. The BSP builds with no errors, it is the application that has the errors.Solved23Views0likes2Comments
Nios V/c issue: no valid Nios V instance
Hi, I have synthesised a Nios V/c (3.0.0)-based SoC on a DE0-Nano board, which was successfully configured using the quartus_pgm command via a Nios V-shell terminal in Quartus Prime Standard 24.1. However, when the niosv-download command is executed after generating BSP and ELF files, the following message appears on the display: ... There are no devices with valid Nios V instance(s) ERROR: Failed to generate OpenOCD config file. ... However, if the same Quartus project is compiled with the Nios V/c (3.0.0) core replaced by a multicycle Nios V/m (26.0.0) core, this error does not appear, and the program runs successfully. Could you please provide any hints on how to fix this error for the Nios V/c IP ? Regards, Domingo.Solved42Views0likes2Comments