Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

Hi Sue,

Thanks for the 2 links .....but neither seem to be very useful to me to be honest. The first one doesn't show anything about an mSGDMA or any other DMA and i can't see any mention of using an mSGDMA on the Agilex 5 example either, plus i don't have an Agilex 5 Premium board or Quartus Prime Pro (i am working with Quartus Standard edition 25.1 and a MAX10 Development board). Thanks for trying though. I will continue my quest !

Best regards,

Dr Barry H

Hi Sue,

No problem.....ALTERA does have a huge database full of just about everything, and i know it is hard to apply the right filters so that you get the right things sometimes (always!).

Yes please if you can point me to that AGILEX 7 + mSGDMA example design and if i can unzip it and see it in a Platform on Quartus it would help to get me started i hope.

Cheers, Dr Barry H

Hi drbarryh 

The link shared by SueC_Altera is the one you are looking for.

It is using the NiosV processor core with the mSGDMA IP. 

It is for the Agilex7 but you could recreate the hardware connections in the project for the device that you want.

Do take note on the naming of the par. It should be top.par and not top(x).par if you have downloaded multiple.

But once you managed to unzip the par, you should go thorugh the IP Upgrade which is prompt when you open the project for the first time.

In the project folder you could see a folder names "sw" in it you could see a main source that you could reference on accesssing the mSGDMA IP from the NiosV processor.

Thanks Sue, yes this text boxing can be picky can't it ! Right the link you sent me worked and i can see an AGILEX 7 example design PAR file and it does at least have DMA in it so that is a better start !

Thanks for the help, Dr Barry H

Hi Sue, unfortunately i installed Quartus Prime Pr version 25.3.1 (the latest) and that failed to unravel the PAR file. I will install the version cited to work which was 24.3.1 and try again ! Also the board used is now showing as obsolete as well.

Any idea if there is another ALTERA example design using a NIOSV processor and the mSGDMA IP core i could use ?
Thanks, Dr Barry H

Greetings Fawaz, Sorry for the delay in replying to your question. I have been battling away trying to get a Triple Speed Ethernet IP core to work in a MAX10 Development kit. This design uses the two mSGDMA engines that are now working, thanks for your help on that DMA area. But i am really stuck on getting a NIOSV/m processor with software to run Ethernet Frames from an ALTERA TSE. 
My setup is as follows:

MAX10DevKit Design :

NIOSV/m + Tx mSGDMA -> TSE  Transmit [SMALL 1G MAC configuration] <- TSE Receive <- Rx mSGDMA 

 RaspberryPI5 <=> Ethernet <=> MAX10 Dev Kit

I have software to initialise both the MARVELL 88E1111 PHY and the TSE in 1G Small MAC Mode

The software uses interrupts as before the Tx mSGDMA and the Rx mSGDMA and this is working because it uses the same approach as my other design which has the mSGDMA loop back working uising two mSGDMA Engines. One configured as Tx mSGDMA :: AVALON-MM -> AVALON-ST ---> AVALON-ST -> AVALON-MM -> Rx:mSGDMA 

What i see is the MARVEL 88E1111 PHY doing  auto negotiation with a RaspberryPI5 and saying LINK UP

But when i try to send any Ethernet frames (i am sending Frames with a IPv4 + TCP Payload), the first thing my software tries to send is a TCP 3 weay handshake, so from the MAX10 FPGA should send a IPv4 + TCP packet with SYN flag set. On the RaspberryPI 5 i use WIRESHARK to detect packets and i never see any packet being sent by the TSE.

If you could help me figure out why the TSE is not working i can send you my entire project (i am using Quartus Lite 25.1 at the moment) as a 7ZIP file to an email address perhaps ? I don;t think i can attach such a larger file to this post can i!

Best regards, Dr Barry H