NiosV µC/OS-II TCP-IP debug
Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devkit, so I compiled it for two different Arria10 targets. For both targets, I get the error: [network_init] Failed to NetIF_Start(): (2010). TSE link seems to be OK. Since I'm not experienced with Nios, I'm looking for help to debug it. Thanks
Unable to transmit out of 16550 Compatible UART
Hi I am following the example of the 16550 Compatible UART in the Embedded peripherals IP User Guide and using the provided code I am not seeing any data in the loopback configuration. Software is Quartus Prime Lite 18.1 Any idea or suggestions is greatly appreciated. I'm not sure if I need to configure any registers?NiosV µC/OS-II
Hello, I try to design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I understand that uC-TCP-IP library needs µC/OS-II but this option is not available in bsp editor GUI (only hal and freertos are available). When I try to execute the command from the project README, I have the following error : $ niosv-bsp -c sw/bsp/settings.bsp -qpf=hw/top.qpf -qsys=hw/sys.qsys --type=ucosii --cmd="enable_sw_package uc_tcp_ip" ... 2026.03.11.18:36:31 Warning: Environment variable SOPC_KIT_NIOS2 not set 2026.03.11.18:36:38 Info: Searching for BSP components with category: os_software_element 2026.03.11.18:36:41 Error: BSP type "ucosii" is not valid. Valid types are: * freertos * hal I'm using Quartus Version 23.4.0 Build 79 11/22/2023 Patches 0.70 SC Pro Edition Thank you for your help.
NIOS interface to HPS in Agilex 5 for communication.
The question is about having NIOS design interacting with HPS of same FPGA. The NIOS would be created as design partition and imported to the HPS project. My understanding is normally this is done through the FPGA2HPS/HPS2FPGA bridge. How this is implemented in project where the NIOS is imported design partition in the HPS project.
Nios-V on Cyclone IV
Hi all Trying to get a NÌOS-V running on Cyclone IV using, just the basics. Using Quartus 25.1. Just as a test I added just the neccessary components and the sysid as shows in the picture below. Quartus project was compiled without any errors. Moving on to the application, created a bsp with the sopcinfo file created by Quartus using the command : niosv-bsp --create --sopcinfo=iwis_top.sopcinfo --type=hal software/bsp/settings.bsp Then created the application using the command : niosv-app --bsp-dir=software/bsp --app-dir=software/app --srcs=software/app The application compiles with "empty" main file, but if I try to add system.h and altera_avalon_sysid_qsys to use alt_avalon_sysid_qsys_test() it failes with error "Unknown reference to alt_avalon_sysid_qsys_test". Should not this work right right out of the box ?Ashling IDE scripted project creation
On Windows, is there a way to script the Ashling IDE project creation (or import an existing project)? I'm trying to clean my project down to the bare minimum for CM/repo purposes (deleting .metadata), and then have an automated way to recreate the project up to the point I can open Ashling RiscFree IDE, point to my (newly recreated) workspace, and then the project is already imported and ready to build, with all my previous settings (include paths, optimizations). Right now, the only way I can get this to work is if I manually click File -> Import and go through that dialog to import my sources from the repo. I need a hands-off way to do this. I looked at the Ashling RiscFree IDE manual, but couldn't find anything.
Nios V Logic Element not include
Hi, Currently, we are using Nios V/m in Max10 (10M08) with Quartus 24.1std. However, we observed that the logic elements for Nios V/m are not reflected in the compilation. We also tried recreating the project, but the issue persists — the logic elements are still not shown or included. Best Regards, QY
Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi all, I am developing on a MAX 10 FPGA (specifically, the 10M25DAF4817G) using the Nios V processor. I need advice on the recommended Quartus Prime Standard Edition version for this workflow.Here is my situation and question: My Target FPGA: Intel MAX 10 (10M25DAF4817G). Reference Design: I started with the official: (Introduction • MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example • Altera Documentation and Resources Center) . The documentation for this example states it is validated with Quartus Prime Standard Edition 23.1. My Experience: In Quartus Prime 23.1, I downloaded this example, made my modifications, and successfully got the design to work on my board.However, when I tried to migrate my project to Quartus Prime 25.1 and followed the same process (specifically, during the "Downloading the Software ELF File" step as per the 3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit • AN 985: Nios V Processor Tutorial • Altera Documentation and Resources Center), I encountered some issues. [Quartus/Nios V] Nios V processor debug failure: "Could not halt the target: timeout occurred" with Quartus 25.1 generated SOF Given that the official design example is validated for 23.1, but a newer tool version (25.1) is available: What is the current community recommendation for the Quartus Prime Standard Edition version for stable Nios V development on MAX 10 FPGAs?Should I stick with 23.1 as the known stable version for my device family?Is 25.1 (or another version) now fully supported and recommended? If so, are there any known migration steps or workarounds for the ELF download issue? Any insights would be greatly appreciated. Thank you.
AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"
Hello Altera Gurus, I am now having much trouble building my projects with the AshlingRISCFree IDE using a NIOSV/m processor on a MAX10 FPGA targeted at a MAX10 Development kit. I am using Quartus Standard edition 25.1 on a Windows 10 PC. The process i am following is this: I created an FPGA top level System Verilog file for a new MAX10 Project. created a Qsys Platform which has a NIOSV/m processor connected to a onchip RAM for program storage and a onchip RAM for the DMA data. Added one mSGDMA engine for transmit data operations Added a second mSGDMA engine for receivedata operations Added two RAM onchip memories for the DMA decsriptors and wired up everything created the address map and interrupt mapping saved and generated the Qsys platform In the top level SV file is loopback the Tx -> RX for the two mSGDMAs Used the niosv-bsp-editor in a niosv console to created a BSP using the Qsys sopcinfo file Generated the BSP, created a simple C main application to configure the mSGDMAs and NIOSV/ m processor etc. Imported both the HAL_BSP and HAL_APP folders using: 'Import NIOS-V CMake Project... In the AshlingRSICFree IDE i can successfully run a 'Build all' and compile the HAL_BSP. BUT When i select the hal_app folder and try to build the Project i get these error messages: 17:37:20 Buildscript generation: hal_app::Default in D:\VAREX_mSGDMA_Eval\software\hal_app\build\Default cmake -DCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=ON -G "Unix Makefiles" "D:\\VAREX_mSGDMA_Eval\\software\\hal_app" CMake Warning: Ignoring extra path from command line: "D:\VAREX_mSGDMA_Eval\software\hal_app" CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. Specify --help for usage, or press the help button on the CMake GUI. Problems : Description Resource Path Location Type CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. hal_app de.marw.cdt.cmake.core.internal.CMakeErrorParser CMake Problem cmake exited with status 1. See CDT global build console for details. hal_app de.marw.cdt.cmake.core.internal.BuildscriptGenerator Buildscript Generation Problem Looking at the hal_bsl folder i can see the CMakeLists.txt is present, it is not present (automatically anyway) in the hal_app folder. I assume it would be if it was part of the BSP generate flow, but it ins't there so i assumed it shouldn't be there (in the hal_app folder i mean). Even if i add it manually then try to do a project build again i then see an error message saying the CmakeCache.txt file has not been created. This seems like a big tools flow mess to me. The Project is automatically setup to use a CMake Compile and CMake Build flow. But its not working. I am trying to use the AshlingRISC IDE GDB Debugger to load my ELF file to the NIOSV processor to allow me to debug my project, but of course because i can't even build it this is impossible. I have tried using niosv cli commands to build my ELF file ...and they seem to work, which means the AshlingRISC IDE is the culprit in the failed IDE build process: Here are my NIOSV cli commands : mSGDMA Test: $ niosv-app --bsp-dir=D:/VAREX_mSGDMA_Eval/software/hal_bsp --app-dir=D:/VAREX_mSGDMA_Eval/software/hal_app --srcs=D:/VAREX_mSGDMA_Eval/software/hal_app/msgdma_loopback.c $ cmake -S D:/VAREX_mSGDMA_Eval/software/hal_app -B D:/VAREX_mSGDMA_Eval/software/hal_app/build -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug $ make -j4 -C D:/VAREX_mSGDMA_Eval/software/hal_app/build After i try and fail to do a project build i can also no loner clean this project, it gets stuck in red with the same error. The only way i can get it back to the start state is : File -> Restart ...this is not great !! Does anybody know why i get these errors and how to fix them please ? : Here i have also linked to an older post here in the knowledge base Claiming that "This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4. and later". This appears to be NOT the case though :) Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface? | Altera Community - 338917 NOTE: I have attached 3 screenshots, 2 show the output from the NIOSV CLI when i run the 3 compile commands. The third one shows what happens when i try to load the ELF file which was created after the 3 Compilation steps run to completion. It looks like the GDB debugger detects the NIOSV/m processor (the 1 hard message) and then promptly crashed during part of the boot process. Does anybody have any ideas about why that might be and what is going on please ? Thanks for any help, Dr Barry HDebug Know-How: Ashling* RiscFree* NIOS® V debug using Command Line
#sharing #debug #niosv Disclaimer: This article is provided as-is for educational purposes only, without warranty of any kind. Use the information at your own risk. Always verify implementations in your specific environment and consult official Altera documentation for production deployments. Introduction When a NIOS V design hangs and the RiscFree Ashling GUI becomes unresponsive, you can still debug effectively using the command line. This guide outlines clear, step-by-step instructions for setting breakpoints and monitoring system behavior using GDB server. Steps 1) Open a terminal and enter: >> niosv-shell 2) Run the following command three times to create three terminals: >> xterm& Terminal 1 is to open a port Terminal 2 is to control breakpoints Terminal 3 is to monitor output print messages 3) TERMINAL#1: Identify the JTAGIDCODE and Start GDB Server irst, display the connected JTAG device: >> jtagconfig Then start the Ashling GDB server and note down the port number (in this case is 38791): >> ash-riscv-gdb-server --auto-detect true --probe-type usb-blaster-2 --tap-number 1 --device 034BB0DD --core-number 0 4) TERMINAL#2: Load the ELF file Launch GDB: >> riscv32-unknown-elf-gdb run.elf Inside the GDB prompt: >> file run.elf >> target remote: 38791 >> load run.elf 5) TERMINAL#3: Run JUART Terminal Use JUART to monitor output: >> juart-terminal -c 1 -d 1 -i 0 This will display system logs, print messages, and output triggered by breakpoints. 6) TERMINAL#2: You may now begin debugging using standard GDB commands. Set a breakpoint: >> break <line number> Continue execution until the breakpoint: >> c Step line-by-line >> n 7) Repeat Step (6) as needed - run, monitor output via JUART, examine behavior, and continue. Tips and observations In some cases, the system hangs only when code runs continuously. This may indicate a insufficient time-to-execute issue. Running commands line-by-line (e.g., using `n`) adds implicit delay between operations, preventing hangs. If continuous execution hangs but step execution does not, consider adding delays such as: >> usleep (<value>) Start with a larger value, then gradually reduce it until the hang reappears to identify the required timing margin. For example, the following operations in the function have been identified as the root cause of insufficient time between issuing rd_word and wr_word: Use a large sleep value first to confirm that adding delay resolves the hang issue. >> #define SLEEP2 10000 If the initial delay proves effective, reduce it step‑by‑step until you find the minimum acceptable value that prevents the hang. >> #define SLEEP2 20 Conclusion This procedure should help you debug NIOS V designs reliably even when the GUI tools fail. Help the community grow—if this article was helpful, please mark it as a solution or give it a kudos so it can reach others.
