Nios-V on Cyclone IV
Hi all Trying to get a NÌOS-V running on Cyclone IV using, just the basics. Using Quartus 25.1. Just as a test I added just the neccessary components and the sysid as shows in the picture below. Quartus project was compiled without any errors. Moving on to the application, created a bsp with the sopcinfo file created by Quartus using the command : niosv-bsp --create --sopcinfo=iwis_top.sopcinfo --type=hal software/bsp/settings.bsp Then created the application using the command : niosv-app --bsp-dir=software/bsp --app-dir=software/app --srcs=software/app The application compiles with "empty" main file, but if I try to add system.h and altera_avalon_sysid_qsys to use alt_avalon_sysid_qsys_test() it failes with error "Unknown reference to alt_avalon_sysid_qsys_test". Should not this work right right out of the box ?
Debug Know-How: Ashling* RiscFree* NIOS® V debug using Command Line
#sharing #debug #niosv Disclaimer: This article is provided as-is for educational purposes only, without warranty of any kind. Use the information at your own risk. Always verify implementations in your specific environment and consult official Altera documentation for production deployments. Introduction When a NIOS V design hangs and the RiscFree Ashling GUI becomes unresponsive, you can still debug effectively using the command line. This guide outlines clear, step-by-step instructions for setting breakpoints and monitoring system behavior using GDB server. Steps 1) Open a terminal and enter: >> niosv-shell 2) Run the following command three times to create three terminals: >> xterm& Terminal 1 is to open a port Terminal 2 is to control breakpoints Terminal 3 is to monitor output print messages 3) TERMINAL#1: Identify the JTAGIDCODE and Start GDB Server irst, display the connected JTAG device: >> jtagconfig Then start the Ashling GDB server and note down the port number (in this case is 38791): >> ash-riscv-gdb-server --auto-detect true --probe-type usb-blaster-2 --tap-number 1 --device 034BB0DD --core-number 0 4) TERMINAL#2: Load the ELF file Launch GDB: >> riscv32-unknown-elf-gdb run.elf Inside the GDB prompt: >> file run.elf >> target remote: 38791 >> load run.elf 5) TERMINAL#3: Run JUART Terminal Use JUART to monitor output: >> juart-terminal -c 1 -d 1 -i 0 This will display system logs, print messages, and output triggered by breakpoints. 6) TERMINAL#2: You may now begin debugging using standard GDB commands. Set a breakpoint: >> break <line number> Continue execution until the breakpoint: >> c Step line-by-line >> n 7) Repeat Step (6) as needed - run, monitor output via JUART, examine behavior, and continue. Tips and observations In some cases, the system hangs only when code runs continuously. This may indicate a insufficient time-to-execute issue. Running commands line-by-line (e.g., using `n`) adds implicit delay between operations, preventing hangs. If continuous execution hangs but step execution does not, consider adding delays such as: >> usleep (<value>) Start with a larger value, then gradually reduce it until the hang reappears to identify the required timing margin. For example, the following operations in the function have been identified as the root cause of insufficient time between issuing rd_word and wr_word: Use a large sleep value first to confirm that adding delay resolves the hang issue. >> #define SLEEP2 10000 If the initial delay proves effective, reduce it step‑by‑step until you find the minimum acceptable value that prevents the hang. >> #define SLEEP2 20 Conclusion This procedure should help you debug NIOS V designs reliably even when the GUI tools fail. Help the community grow—if this article was helpful, please mark it as a solution or give it a kudos so it can reach others.AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"
Hello Altera Gurus, I am now having much trouble building my projects with the AshlingRISCFree IDE using a NIOSV/m processor on a MAX10 FPGA targeted at a MAX10 Development kit. I am using Quartus Standard edition 25.1 on a Windows 10 PC. The process i am following is this: I created an FPGA top level System Verilog file for a new MAX10 Project. created a Qsys Platform which has a NIOSV/m processor connected to a onchip RAM for program storage and a onchip RAM for the DMA data. Added one mSGDMA engine for transmit data operations Added a second mSGDMA engine for receivedata operations Added two RAM onchip memories for the DMA decsriptors and wired up everything created the address map and interrupt mapping saved and generated the Qsys platform In the top level SV file is loopback the Tx -> RX for the two mSGDMAs Used the niosv-bsp-editor in a niosv console to created a BSP using the Qsys sopcinfo file Generated the BSP, created a simple C main application to configure the mSGDMAs and NIOSV/ m processor etc. Imported both the HAL_BSP and HAL_APP folders using: 'Import NIOS-V CMake Project... In the AshlingRSICFree IDE i can successfully run a 'Build all' and compile the HAL_BSP. BUT When i select the hal_app folder and try to build the Project i get these error messages: 17:37:20 Buildscript generation: hal_app::Default in D:\VAREX_mSGDMA_Eval\software\hal_app\build\Default cmake -DCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=ON -G "Unix Makefiles" "D:\\VAREX_mSGDMA_Eval\\software\\hal_app" CMake Warning: Ignoring extra path from command line: "D:\VAREX_mSGDMA_Eval\software\hal_app" CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. Specify --help for usage, or press the help button on the CMake GUI. Problems : Description Resource Path Location Type CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. hal_app de.marw.cdt.cmake.core.internal.CMakeErrorParser CMake Problem cmake exited with status 1. See CDT global build console for details. hal_app de.marw.cdt.cmake.core.internal.BuildscriptGenerator Buildscript Generation Problem Looking at the hal_bsl folder i can see the CMakeLists.txt is present, it is not present (automatically anyway) in the hal_app folder. I assume it would be if it was part of the BSP generate flow, but it ins't there so i assumed it shouldn't be there (in the hal_app folder i mean). Even if i add it manually then try to do a project build again i then see an error message saying the CmakeCache.txt file has not been created. This seems like a big tools flow mess to me. The Project is automatically setup to use a CMake Compile and CMake Build flow. But its not working. I am trying to use the AshlingRISC IDE GDB Debugger to load my ELF file to the NIOSV processor to allow me to debug my project, but of course because i can't even build it this is impossible. I have tried using niosv cli commands to build my ELF file ...and they seem to work, which means the AshlingRISC IDE is the culprit in the failed IDE build process: Here are my NIOSV cli commands : mSGDMA Test: $ niosv-app --bsp-dir=D:/VAREX_mSGDMA_Eval/software/hal_bsp --app-dir=D:/VAREX_mSGDMA_Eval/software/hal_app --srcs=D:/VAREX_mSGDMA_Eval/software/hal_app/msgdma_loopback.c $ cmake -S D:/VAREX_mSGDMA_Eval/software/hal_app -B D:/VAREX_mSGDMA_Eval/software/hal_app/build -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug $ make -j4 -C D:/VAREX_mSGDMA_Eval/software/hal_app/build After i try and fail to do a project build i can also no loner clean this project, it gets stuck in red with the same error. The only way i can get it back to the start state is : File -> Restart ...this is not great !! Does anybody know why i get these errors and how to fix them please ? : Here i have also linked to an older post here in the knowledge base Claiming that "This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4. and later". This appears to be NOT the case though :) Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface? | Altera Community - 338917 NOTE: I have attached 3 screenshots, 2 show the output from the NIOSV CLI when i run the 3 compile commands. The third one shows what happens when i try to load the ELF file which was created after the 3 Compilation steps run to completion. It looks like the GDB debugger detects the NIOSV/m processor (the 1 hard message) and then promptly crashed during part of the boot process. Does anybody have any ideas about why that might be and what is going on please ? Thanks for any help, Dr Barry HCorrect way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA
Greetings all ALTERA Experts, Can somebody please provide some guidance (e.g. links to example designs and App notes etc.) showing how to implement an mSGDMA based system using a NIOSV/m processor on a MAX10 FPGA? The first problem is where to find the best and most up to date Documentation and any example designs actually using the mSGDMA. With clear descriptions of how the data and control flow works, hopefully describing how descriptors are created and then used by the mSGDMA IP cores. Another area of concern is how to wire up mSGDMA IP cores correctly in a Qsys platform (to both data and descriptor memory etc.), and with both the prefetcher and burst mode enabled. I want to use one mSGDMA with an AVALON MM -> AVALON ST flow and a second for AVALON ST -> AVALON MM Flow. Then the next area of concern is how to write a HAL based driver with the NIOSV/m processor to interact with mSGDMA IOP cores. Thanks for any help, Dr Barry H
No valid license for Nios processor
I tried to compile example designs on Altera’s websit. If the design includes a Nios processor, I’d get the following error. Do I need to request a separate license patch for Nios processor? Error(23714): Can not generate programming files for your current project because you do not have a valid license. Visit the Intel FPGA Self-Service Licensing Center at https://licensing.intel.com Warning(115005): Unlicensed IP: "Nios V/g General Purpose Processor Intel FPGA IP (6AF7 018C)" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/auto_fab_0/23.4.0/final/1/netlist.model" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/auto_fab_0/23.4.0/final/1/names.model" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/root_partition/23.4.0/final/1/netlist.model" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/root_partition/23.4.0/final/1/names.model"
Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi all, I am developing on a MAX 10 FPGA (specifically, the 10M25DAF4817G) using the Nios V processor. I need advice on the recommended Quartus Prime Standard Edition version for this workflow.Here is my situation and question: My Target FPGA: Intel MAX 10 (10M25DAF4817G). Reference Design: I started with the official: (Introduction • MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example • Altera Documentation and Resources Center) . The documentation for this example states it is validated with Quartus Prime Standard Edition 23.1. My Experience: In Quartus Prime 23.1, I downloaded this example, made my modifications, and successfully got the design to work on my board.However, when I tried to migrate my project to Quartus Prime 25.1 and followed the same process (specifically, during the "Downloading the Software ELF File" step as per the 3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit • AN 985: Nios V Processor Tutorial • Altera Documentation and Resources Center), I encountered some issues. [Quartus/Nios V] Nios V processor debug failure: "Could not halt the target: timeout occurred" with Quartus 25.1 generated SOF Given that the official design example is validated for 23.1, but a newer tool version (25.1) is available: What is the current community recommendation for the Quartus Prime Standard Edition version for stable Nios V development on MAX 10 FPGAs?Should I stick with 23.1 as the known stable version for my device family?Is 25.1 (or another version) now fully supported and recommended? If so, are there any known migration steps or workarounds for the ELF download issue? Any insights would be greatly appreciated. Thank you.Unable to load Ashling Riscfree NiosV libraries
Hello, I have been trying to make Ashling Riscfree for NiosV debugging work on our Linux system with Quartus v23.1; I have installed RIscFree together with Quartus from the all-in-one data package. Whenever I start RiscFree, Eclipse loads but I see none of the actual plugins for NiosV. This is the .log I see in my workspace: !SESSION 2026-02-13 14:16:09.472 ----------------------------------------------- eclipse.buildId=unknown java.version=20.0.1 java.vendor=Eclipse Adoptium BootLoader constants: OS=linux, ARCH=x86_64, WS=gtk, NL=en_US Command-line arguments: -os linux -ws gtk -arch x86_64 -clean -data /home/laboratorio/workspace_niosv !ENTRY org.eclipse.cdt.core 4 0 2026-02-13 14:22:56.805 !MESSAGE FrameworkEvent ERROR !STACK 0 org.osgi.framework.BundleException: Exception in org.eclipse.cdt.core.CCorePlugin.stop() of bundle org.eclipse.cdt.core. at org.eclipse.osgi.internal.framework.BundleContextImpl.stop(BundleContextImpl.java:895) at org.eclipse.osgi.internal.framework.EquinoxBundle.stopWorker0(EquinoxBundle.java:1046) at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.stopWorker(EquinoxBundle.java:376) at org.eclipse.osgi.container.Module.doStop(Module.java:660) at org.eclipse.osgi.container.Module.stop(Module.java:521) at org.eclipse.osgi.container.ModuleContainer$ContainerStartLevel.decStartLevel(ModuleContainer.java:1893) at org.eclipse.osgi.container.ModuleContainer$ContainerStartLevel.doContainerStartLevel(ModuleContainer.java:1768) at org.eclipse.osgi.container.SystemModule.stopWorker(SystemModule.java:275) at org.eclipse.osgi.internal.framework.EquinoxBundle$SystemBundle$EquinoxSystemModule.stopWorker(EquinoxBundle.java:208) at org.eclipse.osgi.container.Module.doStop(Module.java:660) at org.eclipse.osgi.container.Module.stop(Module.java:521) at org.eclipse.osgi.container.SystemModule.stop(SystemModule.java:207) at org.eclipse.osgi.internal.framework.EquinoxBundle$SystemBundle$EquinoxSystemModule$1.run(EquinoxBundle.java:226) at java.base/java.lang.Thread.run(Thread.java:1623) Caused by: java.lang.NullPointerException: Cannot invoke "org.eclipse.core.runtime.content.IContentTypeManager.removeContentTypeChangeListener(org.eclipse.core.runtime.content.IContentTypeManager$IContentTypeChangeListener)" because the return value of "org.eclipse.core.runtime.Platform.getContentTypeManager()" is null at org.eclipse.cdt.internal.core.model.CModelManager.shutdown(CModelManager.java:1378) at org.eclipse.cdt.core.model.CoreModel.shutdown(CoreModel.java:1156) at org.eclipse.cdt.core.CCorePlugin.stop(CCorePlugin.java:375) at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:875) at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) at java.base/java.security.AccessController.doPrivileged(AccessController.java:571) at org.eclipse.osgi.internal.framework.BundleContextImpl.stop(BundleContextImpl.java:867) ... 13 more Root exception: java.lang.NullPointerException: Cannot invoke "org.eclipse.core.runtime.content.IContentTypeManager.removeContentTypeChangeListener(org.eclipse.core.runtime.content.IContentTypeManager$IContentTypeChangeListener)" because the return value of "org.eclipse.core.runtime.Platform.getContentTypeManager()" is null at org.eclipse.cdt.internal.core.model.CModelManager.shutdown(CModelManager.java:1378) at org.eclipse.cdt.core.model.CoreModel.shutdown(CoreModel.java:1156) at org.eclipse.cdt.core.CCorePlugin.stop(CCorePlugin.java:375) at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:875) at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) at java.base/java.security.AccessController.doPrivileged(AccessController.java:571) at org.eclipse.osgi.internal.framework.BundleContextImpl.stop(BundleContextImpl.java:867) at org.eclipse.osgi.internal.framework.EquinoxBundle.stopWorker0(EquinoxBundle.java:1046) at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.stopWorker(EquinoxBundle.java:376) at org.eclipse.osgi.container.Module.doStop(Module.java:660) at org.eclipse.osgi.container.Module.stop(Module.java:521) at org.eclipse.osgi.container.ModuleContainer$ContainerStartLevel.decStartLevel(ModuleContainer.java:1893) at org.eclipse.osgi.container.ModuleContainer$ContainerStartLevel.doContainerStartLevel(ModuleContainer.java:1768) at org.eclipse.osgi.container.SystemModule.stopWorker(SystemModule.java:275) at org.eclipse.osgi.internal.framework.EquinoxBundle$SystemBundle$EquinoxSystemModule.stopWorker(EquinoxBundle.java:208) at org.eclipse.osgi.container.Module.doStop(Module.java:660) at org.eclipse.osgi.container.Module.stop(Module.java:521) at org.eclipse.osgi.container.SystemModule.stop(SystemModule.java:207) at org.eclipse.osgi.internal.framework.EquinoxBundle$SystemBundle$EquinoxSystemModule$1.run(EquinoxBundle.java:226) at java.base/java.lang.Thread.run(Thread.java:1623) I have tried making a "clean" run of RiscFree, by using the following custom .sh: #!/bin/bash # --- Definizione Percorsi --- # Usiamo il percorso che hai indicato tu nei messaggi precedenti export QUARTUS_INSTALL_DIR=/opt/intelFPGA_pro/Quartus23.1 export QUARTUS_ROOTDIR=$QUARTUS_INSTALL_DIR/quartus export NIOSV_HOME=$QUARTUS_INSTALL_DIR/niosv # --- Configurazione Ambiente --- # Aggiungiamo i binari di Quartus e Nios V al PATH export PATH=$QUARTUS_ROOTDIR/bin:$NIOSV_HOME/bin:$PATH # Variabili fondamentali per i plugin Ashling export RISCV_JET_PATH=$NIOSV_HOME/bin # --- Risoluzione problemi grafici MobaXterm/X11 --- export NO_AT_BRIDGE=1 # Se l'interfaccia dovesse apparire vuota o nera, prova a cambiare 0 con 1 qui sotto export SWT_GTK3=0 # --- Avvio IDE --- echo "Inizializzazione ambiente Nios V e avvio RiscFree..." cd $QUARTUS_INSTALL_DIR/riscfree/RiscFree/ ./RiscFree -clean -data ~/workspace_niosv & But this has changed absolutely nothing. It is impossible to see NIOS V or Ashling RiscFree integration in the RiscFree environment. What could be the issue? I will now add a few infos about our system. uname -r : 5.15.0-139-generic cat /etc/os-release: NAME="Ubuntu" VERSION="20.04.6 LTS (Focal Fossa)" ID=ubuntu ID_LIKE=debian PRETTY_NAME="Ubuntu 20.04.6 LTS" VERSION_ID="20.04" HOME_URL="https://www.ubuntu.com/" SUPPORT_URL="https://help.ubuntu.com/" BUG_REPORT_URL="https://bugs.launchpad.net/ubuntu/" PRIVACY_POLICY_URL="https://www.ubuntu.com/legal/terms-and-policies/privacy-policy" VERSION_CODENAME=focal UBUNTU_CODENAME=focal I am worried JAVA might be causing issues but I have not been able to solve them.
NIOS does not start after SW download (timing issue?)
Hi, Recently I got an old Arria V design to update. It is in Quartus II 15.0 containing the following main components (in Qsys design): NIOS II soft processor 2x UniPHY DDR3 RAM controller (soft version, not hard), 72 bit wide data running at 400MHz clock (800Mb/s) 2x Triple Speed Ethernet with 4x SGDMA The design uses only 40k ALMs out of 190k so it fits well but I have timing issues (slack) on pll_afi_clk for one or both DDR3 controllers. I can reduce it by a lot of fine tuning on synthesizer and fitter settings but when I change a bit in the design timing results go wrong and tuning has to be started again. Both FW and SW are downloaded to SRAM by ByteBlaster. I found when the slacks are big (>0.1ns) NIOS never starts after downloading the SW. When it is small or completely eliminated, NIOS starts in most of the cases (but not always). Is this normal for such a design, or am I doing something wrong? I have never seen such behaviour before. Can this timing issue affect the NIOS processor on such a way or should I search in another direction to solve the problem?Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,
