NIOS II "Verify failed" for on-chip memory 128k
Hello! I'm using a Cyclone 10LP FPGA 10CL055YU484I7G FPGA. I have a 11k size program for NIOS II. I have a large on chip RAM (because I have a larger program which I want to use later) of 128k. Everything compiles and links OK. But when I try to download the program I get a "Verify failed between address 0x20000 and 0x2FFFF". The 128K memory is located 0x20000 to 0x3FFFF If I reduce the RAM to 32K, for example, everything works great!!. The initialize memory content option is turned on for the memory The BOOT RAM starts at 0x00000 If I download a bigger program (117k), I still get the same error. Thanks
NIOS-V QSYS Warning Properties (associatedClock) have been set on
Hello, I have a really basic setup of a NIOS V system, but get Warnings in QSYS (using Quartus 25.1 Standard) about Properties of associatedClock: System: Warning: Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock) have been set on interface reset - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface instruction_manager - in composed mode these are ignored Warning: nios_subsystem.intel_niosv_m_0: Properties (associatedClock,associatedReset) have been set on interface data_manager - in composed mode these are ignored Questions: What is "composed mode" and how can I control it? There is no NIOS Parameter associated with it This appears in a basic setup simply by adding NIOS V to the system. How do I get rid of this warning? best regards Fabian
DK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails
Hello, I am using the following board and host environment: Board: Agilex 7 FPGA I-Series Development Kit, DK-DEV-AGI027-RA Serial number: 8100604 Quartus Prime Pro: 25.3.1 Host OS: Windows 11 Pro Before this issue, the board was working normally with CXL ED and PCIe designs. Issue summary After successfully running a modified version of the "Nios V Hello" tutorial design (SOF + ELF) on this kit, Quartus Programmer can no longer detect the JTAG chain reliably. "Auto Detect" fails, and the JTAG Chain Debugger reports unknown devices and possible JTAG signal issues. Steps and observations 1. I modified the Nios V Hello tutorial design (SOF + ELF), including pin assignments and power management & SmartVID assignments, to match DK-DEV-AGI027-RA. Programming completed successfully, and I confirmed the expected "Hello" output. After that first run, I attempted to download an updated SOF, but Quartus Programmer "Auto Detect" failed. JTAG Chain Debugger screenshot: Programmer/Debugger log: !Error: JTAG chain problem detected !Error: TDI connection to the first detected device UNKNOWN_00000001 might be shorted to GND !Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_00000001 might have a problem !Info: Detected 2 device(s) !Info: Device 1: UNKNOWN_00000001 !Info: Device 2: UNKNOWN_020D10DD Recovery attempts and results 2. Connected an external USB-Blaster II to J10, set SW8.3 = ON, and completed MAX10 recovery successfully. 3. Set SW8.3 = OFF to attempt FPGA recovery. Quartus Programmer Auto Detect still failed. 4. Loaded the predefined fpga_recovery.cdf and attempted to program AVSTX8.pof, but it failed with: Error(209062): Flash Loader IP not loaded on device 2 Error(209012): Operation failed 5. Set SW8.2 = ON to remove the FPGA from the JTAG chain, then successfully programmed AVSTX8.pof into QSPI. 6. Set SW8.2 = OFF again, but Auto Detect still failed. 7. Removed the external USB-Blaster II and tried the embedded JTAG interface. Auto Detect still failed. Questions. Are there additional recommended steps beyond MAX10 recovery and programming the recovery POF to QSPI (for example, specific switch combinations, a required full power-cycle sequence, or other board-level recovery steps)? If MAX10 recovery completes but JTAG remains broken on both external and embedded JTAG, does this suggest a likely hardware issue (JTAG path, FPGA, or related circuitry) that requires RMA? Is there anything in the Nios V Hello tutorial flow that could plausibly cause this condition (for example, power management settings, pin assignments, or JTAG-related settings)? If needed, I can share additional logs, exact switch settings, and any other diagnostics you recommend. Thanks.
Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,Unable to transmit out of 16550 Compatible UART
Hi I am following the example of the 16550 Compatible UART in the Embedded peripherals IP User Guide and using the provided code I am not seeing any data in the loopback configuration. Software is Quartus Prime Lite 18.1 Any idea or suggestions is greatly appreciated. I'm not sure if I need to configure any registers?
Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi all, I am developing on a MAX 10 FPGA (specifically, the 10M25DAF4817G) using the Nios V processor. I need advice on the recommended Quartus Prime Standard Edition version for this workflow.Here is my situation and question: My Target FPGA: Intel MAX 10 (10M25DAF4817G). Reference Design: I started with the official: (Introduction • MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example • Altera Documentation and Resources Center) . The documentation for this example states it is validated with Quartus Prime Standard Edition 23.1. My Experience: In Quartus Prime 23.1, I downloaded this example, made my modifications, and successfully got the design to work on my board.However, when I tried to migrate my project to Quartus Prime 25.1 and followed the same process (specifically, during the "Downloading the Software ELF File" step as per the 3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit • AN 985: Nios V Processor Tutorial • Altera Documentation and Resources Center), I encountered some issues. [Quartus/Nios V] Nios V processor debug failure: "Could not halt the target: timeout occurred" with Quartus 25.1 generated SOF Given that the official design example is validated for 23.1, but a newer tool version (25.1) is available: What is the current community recommendation for the Quartus Prime Standard Edition version for stable Nios V development on MAX 10 FPGAs?Should I stick with 23.1 as the known stable version for my device family?Is 25.1 (or another version) now fully supported and recommended? If so, are there any known migration steps or workarounds for the ELF download issue? Any insights would be greatly appreciated. Thank you.
NIOS does not start after SW download (timing issue?)
Hi, Recently I got an old Arria V design to update. It is in Quartus II 15.0 containing the following main components (in Qsys design): NIOS II soft processor 2x UniPHY DDR3 RAM controller (soft version, not hard), 72 bit wide data running at 400MHz clock (800Mb/s) 2x Triple Speed Ethernet with 4x SGDMA The design uses only 40k ALMs out of 190k so it fits well but I have timing issues (slack) on pll_afi_clk for one or both DDR3 controllers. I can reduce it by a lot of fine tuning on synthesizer and fitter settings but when I change a bit in the design timing results go wrong and tuning has to be started again. Both FW and SW are downloaded to SRAM by ByteBlaster. I found when the slacks are big (>0.1ns) NIOS never starts after downloading the SW. When it is small or completely eliminated, NIOS starts in most of the cases (but not always). Is this normal for such a design, or am I doing something wrong? I have never seen such behaviour before. Can this timing issue affect the NIOS processor on such a way or should I search in another direction to solve the problem?Ashling IDE scripted project creation
On Windows, is there a way to script the Ashling IDE project creation (or import an existing project)? I'm trying to clean my project down to the bare minimum for CM/repo purposes (deleting .metadata), and then have an automated way to recreate the project up to the point I can open Ashling RiscFree IDE, point to my (newly recreated) workspace, and then the project is already imported and ready to build, with all my previous settings (include paths, optimizations). Right now, the only way I can get this to work is if I manually click File -> Import and go through that dialog to import my sources from the repo. I need a hands-off way to do this. I looked at the Ashling RiscFree IDE manual, but couldn't find anything.
