Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)

Hi all,
I am developing on a MAX 10 FPGA (specifically, the 10M25DAF4817G) using the Nios V processor. I need advice on the recommended Quartus Prime Standard Edition version for this workflow.Here is my situation and question:

My Target FPGA:​ Intel MAX 10 (10M25DAF4817G).

Reference Design:​ I started with the official: (Introduction • MAX® 10 FPGA - Helloworld on Nios® V/m Processor Design Example • Altera Documentation and Resources Center)

. The documentation for this example states it is validated with Quartus Prime Standard Edition 23.1​.

My Experience:

In Quartus Prime 23.1, I downloaded this example, made my modifications, and successfully got the design to work on my board.However, when I tried to migrate my project to Quartus Prime 25.1​ and followed the same process (specifically, during the "Downloading the Software ELF File" step as per the 3. Hello World on MAX 10 FPGA 10M50 Evaluation Kit • AN 985: Nios V Processor Tutorial • Altera Documentation and Resources Center), I encountered some issues.

[Quartus/Nios V] Nios V processor debug failure: "Could not halt the target: timeout occurred" with Quartus 25.1 generated SOF

Given that the official design example is validated for 23.1, but a newer tool version (25.1) is available:

What is the current community recommendation for the Quartus Prime Standard Edition version for stable Nios V development on MAX 10 FPGAs?Should I stick with 23.1​ as the known stable version for my device family?Is 25.1​ (or another version) now fully supported and recommended? If so, are there any known migration steps or workarounds for the ELF download issue?

Any insights would be greatly appreciated.

Thank you.